Patent application number | Description | Published |
20090072013 | NANO-SCALE PARTICLE PASTE FOR WIRING MICROELECTRONIC DEVICES USING INK-JET PRINTING - Nano-scale particle paste may be used for on-die routing and other applications using deposition and inkjet printing. A metal paste is applied to a surface of a die to electrically couple two spaced apart connection points of the die. Alternatively, or in addition, the paste may contain carbon nanotubes. The paste may be used on other surfaces as well. | 03-19-2009 |
20090109643 | THIN SEMICONDUCTOR DEVICE PACKAGE - A thin semiconductor device package, comprising a thin substrate at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end. | 04-30-2009 |
20090320281 | Apparatus and methods of forming package-on-package interconnects - Embodiments of an apparatus and methods of forming a package on package interconnect and its application to the packaging of microelectronic devices are described herein. Other embodiments may be described and claimed. | 12-31-2009 |
20100258927 | Package-on-package interconnect stiffener - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. | 10-14-2010 |
20100309704 | In-pakage microelectronic apparatus, and methods of using same - A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s. | 12-09-2010 |
20130292838 | PACKAGE-ON-PACKAGE INTERCONNECT STIFFENER - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. | 11-07-2013 |
20140167217 | PACKAGE WITH DIELECTRIC OR ANISOTROPIC CONDUCTIVE (ACF) BUILDUP LAYER - Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed. | 06-19-2014 |
Patent application number | Description | Published |
20080295325 | MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS - The formation of electronic assemblies, including assemblies having an interposer, are described. In one embodiment, a method includes forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface of the body, the electrically conductive layer defining a first metal pad layer on the upper surface and a second metal pad layer in contact with the first metal pad layer, the second metal pad layer having a denser pitch between adjacent pads than the first metal pad layer. The method also includes forming a dielectric layer between the adjacent metal pads in the first and second pad layers. The method also includes coupling a plurality of elements to the second metal pad layer. After the coupling the elements, the method includes thinning the body through a lower surface and exposing the electrically insulating layer in the vias. The method also includes removing a portion of the electrically insulating layer in the vias, and coupling the electrically conductive layer to a substrate, wherein the body is positioned between the elements and the substrate. Other embodiments are described and claimed. | 12-04-2008 |
20080295329 | MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS - The formation of electronic assemblies, including assemblies having an interposer, are described. In one embodiment, a method includes providing a body and forming a first metal pad layer on a first surface thereof. A second metal pad layer is formed in contact with the first patterned metal pad layer, the second metal pad layer having a denser pitch between adjacent pads than the first metal pad layer. A dielectric layer is formed between the adjacent metal pads in the first and second metal pad layers. After the forming the first and second metal pad layers and the dielectric layer, the method includes forming a plurality of vias extending through the body from a second surface thereof, the vias extending through a thickness of the body and exposing the first metal pad layer. The method also includes forming an insulating layer on sidewalls of the vias and on the second surface, and forming an electrically conductive layer on the insulating layer and on the exposed surface of the first metal layer. The method also includes coupling a plurality of elements to the second metal pad layer and coupling the electrically conductive layer to a substrate, the body being positioned between the elements and the substrate. Other embodiments are described and claimed. | 12-04-2008 |
20120112336 | ENCAPSULATED DIE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF MANUFACTURING SAID MICROELECTRONIC PACKAGE - An encapsulated die ( | 05-10-2012 |
20120113704 | IN-PACKAGE MICROELECTRONIC APPARATUS, AND METHODS OF USING SAME - A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s. | 05-10-2012 |
20140264951 | LASER DIE BACKSIDE FILM REMOVAL FOR INTEGRATED CIRCUIT (IC) PACKAGING - Embodiments of the present disclosure are directed to die adhesive films for integrated circuit (IC) packaging, as well as methods for forming and removing die adhesive films and package assemblies and systems incorporating such die adhesive films. A die adhesive film may be transparent to a first wavelength of light and photoreactive to a second wavelength of light. In some embodiments, the die adhesive film may be applied to a back or “inactive” side of a die, and the die surface may be detectable through the die adhesive film. The die adhesive film may be cured and/or marked with laser energy having the second wavelength of light. The die adhesive film may include a thermochromic dye and/or nanoparticles configured to provide laser mark contrast. UV laser energy may be used to remove the die adhesive film in order to expose underlying features such as TSV pads. | 09-18-2014 |