Patent application number | Description | Published |
20100095906 | WATER HEATER WITH PARTIALLY THERMALLY ISOLATED TEMPERATURE SENSOR - A water heater having a water tank and a heating source disposed proximate to the water tank such that the heating source may heat water within the water tank. A temperature sensor is provided that is partially thermally isolated from the water in the water tank. A controller may be provided that at least partially compensates for the partial thermal isolation of the temperature sensor and regulates the heating source. In some instances, the temperature sensor may be at least partially disposed within a thermally isolating mass. | 04-22-2010 |
20100116224 | WATER HEATER WITH TEMPORARY CAPACITY INCREASE - A water heater may be configured to temporarily increase its hot water capacity by heating water to a higher boost temperature. In some instances, the water heater may include a main controller that can accept a boost request from a remote controller, and thus may temporarily provide additional hot water capacity without, for example, requiring a homeowner to go down to the basement, out to the garage, or wherever the water heater happens to be to make manual adjustments to the water heater settings. | 05-13-2010 |
20110048340 | HEAT BALANCING SYSTEM - A heat balancing system for a natural draft gas burning appliance having a flue. When the appliance is in a standby mode, a main burner is shut off and the pilot light remains on. Temperature in the heat exchanger (e.g., temperature of water in a heater tank) may be decreased or increased, respectively, by opening or closing a damper in a flue as needed. If opening the damper does not sufficiently reduce the temperature of the heat exchanger, then the pilot light may be shut off to further reduce the temperature. The pilot light may be turned on again to bring up the temperature. There may be a control or controller to operate the damper to maintain the temperature of the exchanger within a certain range. Electrical power may be provided for the system from a power line, a storage device, or other source. | 03-03-2011 |
20110054711 | DAMPER CONTROL SYSTEM - A damper control system having energy efficient mechanisms. The system may use a heat-to-electric power converter such as a thermopile. Heat may come from a pilot light used for igniting a flame for an appliance. The system may store electric energy in a storage module which could be a sufficiently large capacitor. The system may monitor the position of a damper in a vent or the like and provide start and stop movements of the damper using minimal energy. One way that the system may control electrical energy to a damper motor or another electrical mover of the damper is to use pulse width modulated signals. | 03-03-2011 |
20110270544 | STORAGE DEVICE ENERGIZED ACTUATOR HAVING DIAGNOSTICS - A system having unified diagnostics where an electrical energy storage device may supply an actuator. Various techniques may be used to determine energy storage capacity and actuator current usage. Measured storage capacity and actuator current may indicate the health of the energy storage device and the actuator, respectively. Also, operation of a service switch for the actuator may be checked relative to its state. | 11-03-2011 |
Patent application number | Description | Published |
20090070400 | CARRY-SELECT ADDER - A carry select adder to add two binary addends to produce a binary sum. In a first section a first addition block adds 6-bit addend slices having 3-bit lower-half and higher-half slices. A first adder block receives and adds the lower-half slices and outputs an adder-carry-out and a 3-bit lower-half value. A zero-carry-loaded second adder block receives and adds the higher-half slices and outputs a 4-bit zero-related intermediate-value. A one-carry-loaded third adder block receives and adds the higher-half slices and outputs a 4-bit one-related intermediate-value. A 4-bit multiplexer then passes either the zero-related intermediate-value or the one-related intermediate-value as a 1-bit section-carry-out and a 3-bit higher-half value based on the adder-carry-out, wherein the higher-half value and the lower-half value form a 6-bit sum slice corresponding to the 6-bit addend slices. | 03-12-2009 |
20090292757 | Method and apparatus for zero prediction - A zero prediction method and apparatus for use in a reduced instruction set computer. The zero predictor | 11-26-2009 |
20100023730 | Circular Register Arrays of a Computer - The invention provides a method and apparatus for eliminating the stack overflow and underflow in a dual stack computer | 01-28-2010 |
20100088083 | Method and Apparatus for Circuit Simulation - A method of integrated circuit simulation comprising the steps of providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type. Providing a temperature lookup table having predetermined temperature data. Providing a transistor lookup table having predetermined current and temperature data. Simulating operation of an integrated circuit by, for each transistor in the integrated circuit, determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and comparing the current value calculated to the current value obtained previously; and updating active transistor list detecting a change in the current value. Then incrementing a simulation time step and repeating simulation steps for all transistors. Simulating operation of an integrated circuit by, for each transistor in the integrated circuit, determining a transistor temperature value for all transistors in the active transistor list. | 04-08-2010 |
20100138618 | Priority Encoders - A priority encoder and a processing device having the priority encoder. The priority encoder includes a port selector for generating a plurality of prioritized read requests based on a plurality of write requests from a plurality of processing devices and a predetermined priority assigned to each of the plurality of processing devices, one of the plurality of processing devices being selected based on the plurality of prioritized read requests; and a port latch for holding the values of the prioritized read requests to enable one of a plurality of communication ports unless the prioritized read requests are changed, each communication port for communicating with one of the processing devices to read data from the processing device. | 06-03-2010 |