Patent application number | Description | Published |
20080268653 | METHOD OF FORMING HIGH DIELECTRIC FILM USING ATOMIC LAYER DEPOSITION AND METHOD OF MANUFACTURING CAPACITOR HAVING THE HIGH DIELECTRIC FILM - A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor. | 10-30-2008 |
20090050210 | Methods for Operating Liquid Chemical Delivery Systems Having Recycling Elements - Liquid chemical delivery systems are provided which include a liquid chemical storage canister, a pressurized gas source that feeds a pressurized gas into the storage canister, a vaporizer that may be used to vaporize the liquid chemical supplied from the storage canister, a delivery line that connects the storage canister to the vaporizer, a liquid mass flow controller that controls the flow rate of the liquid chemical through the delivery line, a reaction chamber that is connected to the vaporizer, and a liquid chemical recycling element that collects at least some of the chemical flowing through the system during periods when the liquid chemical delivery system is isolated from the reaction chamber. | 02-26-2009 |
20090072350 | SEMICONDUCTOR DEVICES HAVING A CONTACT PLUG AND FABRICATION METHODS THEREOF - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole. | 03-19-2009 |
20100203692 | METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND RELATED DEVICES - A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the PMOS region to exert compressive stress on a first channel region therebetween adjacent the first gate pattern. N-type source/drain regions are epitaxially grown on opposite sides of the second gate pattern in the NMOS region to exert tensile stress on a second channel region therebetween adjacent the second gate pattern. Related devices are also discussed. | 08-12-2010 |
20120088360 | Methods of Fabricating Semiconductor Devices - Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer. | 04-12-2012 |
Patent application number | Description | Published |
20100190320 | METHODS OF REMOVING WATER FROM SEMICONDUCTOR SUBSTRATES AND METHODS OF DEPOSITING ATOMIC LAYERS USING THE SAME - Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate. | 07-29-2010 |
20130005110 | Method of fabricating semiconductor device - Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer. | 01-03-2013 |
20130115760 | METHOD OF FORMING A THIN LAYER STRUCTURE - A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets. | 05-09-2013 |
20130170784 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a single crystalline substrate, an electrical element and an optical element. The electrical element is disposed on the single crystalline substrate. The electrical element includes a gate electrode extending in a crystal orientation <110> and source and drain regions adjacent to the gate electrode. The source region and the drain region are arranged in a direction substantially perpendicular to a direction in which the gate electrode extends. The optical element is disposed on the single crystalline substrate. The optical element includes an optical waveguide extending in a crystal orientation <010>. | 07-04-2013 |
20130213910 | BOAT FOR LOADING SEMICONDUCTOR SUBSTRATES - Provided is a boat for loading semiconductor substrates that includes a top plate and a bottom plate separated from each other, a rod extending from the bottom plate to the top plate and disposed between the top plate and the bottom plate, a plurality of buffer plates disposed between the top plate and the bottom plate and separated from each other by a first distance along a lengthwise direction of the rod, and a support provided between a first buffer plate and a second buffer plate which neighbor each other and supporting a loaded semiconductor substrate. | 08-22-2013 |
20140144380 | GAS SUPPLY PIPES AND CHEMICAL VAPOR DEPOSITION APPARATUS - A gas supply pipe and a chemical vapor deposition (CVD) apparatus including the gas supply pipe. The gas supply pipe includes: a first pipe connected to a gas storage apparatus via a gas supply line to supply a reacting gas into a reacting furnace; and a second pipe thermally contacting the first pipe to cool the first pipe, wherein a first end of the second pipe is connected to a cooling medium supplying unit via a cooling medium line such that a cooling medium circulates inside the second pipe, and a second, opposite end of the second pipe is connected to a cooling medium collecting unit. | 05-29-2014 |
20140256117 | METHODS OF FORMING EPITAXIAL LAYERS - A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer. | 09-11-2014 |
Patent application number | Description | Published |
20080286927 | NON-VOLATILE MEMORY DEVICE WITH BURIED CONTROL GATE AND METHOD OF FABRICATING THE SAME - In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation. | 11-20-2008 |
20090068917 | Apparatus of encapsulating display panel and method of manufacturing organic light emitting display device using the same - An encapsulation apparatus capable of securely sealing a gap of a display panel and improving intensity of the display panel, and a method of manufacturing an organic light emitting display device using the encapsulation apparatus are taught. The encapsulation apparatus includes an injection port having tapered projecting edges formed in both sides of one end the injection port, and injecting a reinforcing material into a gap of a display panel in a dual surface contact manner, the first substrate and the second substrate being attached to each other using a sealant; and a supporter coupled to the injection port and supporting the injection port. | 03-12-2009 |
20090085075 | METHOD OF FABRICATING MOS TRANSISTOR AND MOS TRANSISTOR FABRICATED THEREBY - A method of fabricating a MOS transistor, and a MOS transistor fabricated by the method. The method can include forming a gate pattern on a semiconductor substrate. The gate pattern can be formed by sequentially stacking a gate electrode and a capping layer pattern. The capping layer pattern is formed to have a lower capping layer pattern and an upper capping layer pattern. The lower capping layer pattern is formed to a smaller width than the upper capping layer pattern. | 04-02-2009 |
20090085125 | MOS transistor and CMOS transistor having strained channel epi layer and methods of fabricating the transistors - Provided are a metal oxide semiconductor (MOS) transistor and a complementary MOS (CMOS) transistor each having a strained channel epi layer, and methods of fabricating the transistors. The MOS transistor may include at least one active region defined by an isolation structure formed in a substrate. At least one channel trench may be formed in a part of the at least one active region. At least one strained channel epi layer may be in the at least one channel trench. At least one gate electrode may be aligned on the at least one strained channel epi layer. Sources/drains may be arranged in the at least one active region along both sides of the at least one strained channel epi layer. | 04-02-2009 |
20090203182 | Method of manufacturing transistor having metal silicide and method of manufacturing a semiconductor device using the same - In a method of manufacturing a transistor and a method of manufacturing a semiconductor device using the same, the method may include forming a preliminary metal silicide pattern on a single-crystalline silicon substrate and on a polysilicon pattern, and partially etching the preliminary metal silicide pattern to form a first metal silicide pattern on the substrate and a second metal silicide pattern on the polysilicon pattern, the second metal silicide pattern having a line width the same as or smaller than that of the polysilicon pattern. The method may include the transistor having no metal silicide residue on the spacer. Accordingly, an operation failure due to the residue may be prevented or reduced. | 08-13-2009 |
20100065919 | Semiconductor Devices Including Multiple Stress Films in Interface Area - A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described. | 03-18-2010 |
20120273127 | APPARATUS OF ENCAPSULATING DISPLAY PANEL AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE USING THE SAME - An encapsulation apparatus capable of securely sealing a gap of a display panel and improving intensity of the display panel, and a method of manufacturing an organic light emitting display device using the encapsulation apparatus are taught. The encapsulation apparatus includes an injection port having tapered projecting edges formed in both sides of one end the injection port, and injecting a reinforcing material into a gap of a display panel in a dual surface contact manner, the first substrate and the second substrate being attached to each other using a sealant; and a supporter coupled to the injection port and supporting the injection port. | 11-01-2012 |