Patent application number | Description | Published |
20110095805 | LEVEL SHIFTERS AND INTEGRATED CIRCUITS THEREOF - An integrated circuit includes a level shifter configured to receive a first voltage signal that swings between a first voltage level and a second voltage level, outputting a second voltage signal that swings between the first voltage level and a third voltage level. The third voltage level is higher than the second voltage level. An inverter is coupled with the level shifter. The inverter can receive the second voltage, outputting a third voltage signal that swings between the third voltage level and a fourth voltage level. The fourth voltage level is lower than the third voltage level and higher than the first voltage level. | 04-28-2011 |
20120212279 | Threshold Voltage Detection Apparatus - A threshold voltage detection apparatus comprises a voltage level up-shifter and a voltage level down-shifter. The threshold voltage detection apparatus is placed at a circuit fabricated in a low voltage semiconductor process. The threshold voltage detection apparatus receives an input signal having a wide range and generates output signals comprising the logic of the input signal, but having a voltage range suitable for the low voltage circuit. The threshold voltage detection apparatus ensures that the low voltage circuit operates in a range to which the low voltage semiconductor process is specified. | 08-23-2012 |
20130050885 | ESD PROTECTION TECHNIQUES - Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit that is electrically connected to first and second circuit nodes from an ESD event. The ESD protection device includes a first electrical path extending between the first and second circuit nodes and including first and second ESD detection elements arranged thereon. The ESD protection device also includes first and second voltage bias elements having respective inputs electrically connected to respective outputs of the first and second ESD detection elements. A second electrical path extends between the first and second circuit nodes and is in parallel with the first electrical path. The second electrical path includes a voltage controlled shunt network having at least two control terminals electrically connected to respective outputs of the first and second voltage bias elements. Other embodiments are also disclosed. | 02-28-2013 |
20130170080 | ESD PROTECTION CIRCUIT CELL - A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd | 07-04-2013 |
20130181741 | LEVEL SHIFTERS AND INTEGRATED CIRCUITS THEREOF - An integrated circuit including a first level shifter configured to receive a first input signal and a first power supply signal, and to output a first output signal. The integrated circuit further includes a first inverter configured to receive the first output signal, and to output a first inverter signal. The integrated circuit further includes a second level shifter configured to receive a second input signal and a second power supply signal, and to output a second output signal, wherein a voltage level of the second power supply signal is different from a voltage level of the first power supply signal. The integrated circuit further includes a second inverter configure to receive the second output signal, and to output a second inverter signal. The integrated circuit further includes an output buffer configured to receive the first inverter signal and the second inverter signal, and to output a buffer output signal. | 07-18-2013 |
20140151809 | APPARATUS FOR ESD PROTECTION - A structure comprises an N+ region formed over a substrate, a P+ region formed over the substrate, wherein the P+ region and the N+ region form a diode and a first epitaxial growth block region formed between the N+ region and the P+ region. | 06-05-2014 |
20140175551 | Apparatus for ESD Protection - A structure comprises an N+ region formed over a first fin of a substrate, a P+ region formed over a second fin of the substrate, wherein the P+ region and the N+ region form a diode, a shallow trench isolation region formed between the P+ region and the N+ region and a first epitaxial growth block region formed over the shallow trench isolation region and between the N+ region and the P+ region, wherein a forward bias current of the diode flows through a path underneath the shallow trench isolation region. | 06-26-2014 |
20140210014 | METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED RESISTOR IN A STANDARD CELL CONFIGURATION - An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor. | 07-31-2014 |
20140252476 | Rotated STI Diode on FinFET Technology - A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode. | 09-11-2014 |
20150249080 | METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED RESISTOR IN A STANDARD CELL CONFIGURATION - An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor. | 09-03-2015 |
20150270260 | ESD PROTECTION CIRCUIT CELL - A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd | 09-24-2015 |
20150311192 | Apparatus for ESD Protection - A method comprises forming an active region including a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by an isolation region, depositing an epitaxial growth block layer over the active region, patterning the epitaxial growth block layer to define a first growth area and a second growth area and growing an N+ region in the first growth area and a P+ region in the second growth area. | 10-29-2015 |
Patent application number | Description | Published |
20140082953 | Liquid Capacitive Micro Inclinometer - The present invention relates to a liquid capacitive micro inclinometer, comprising a pair of differential electrodes and a common electrode, all formed in the same plane in a sealed chamber. Immersing liquid is filled in the sealed chamber. The shape of the differential electrodes forms a sector of a circular plane. The inclinometer may further integrate a reading circuit. The present invention also discloses preparation method for the invented inclinometer. | 03-27-2014 |
20140082954 | Multilayered Liquid Capacitive Micro Inclinometer - The present invention relates to a liquid multilayer capacitive micro inclinometer, comprising at least two pairs of differential electrodes, each pair positioned in a same plane; at least one common electrode with a portion positioned in the plane of each pair of differential electrodes. The differential electrodes and the common electrode are provided in a sealed chamber, in which an immersing liquid is filled. The shape of the differential electrodes forms a sector of a circular plane. The inclinometer may further integrate a reading circuit. The present invention also discloses preparation method for the invented inclinometer. | 03-27-2014 |
20140256077 | Method for preparation of micro electro-mechanical structure - The present invention discloses an adhesive-free method for preparation of micro electro-mechanical structure, comprising forming a micro electro-mechanical structure on a first substrate, forming an enclosing space for immersing liquid on the first or second substrate, and applying pressure to fix the first and second substrate. Before applying the pressure, the assembly including the two substrates is flipped, to make the contact surface immersed by the immersing liquid. | 09-11-2014 |
Patent application number | Description | Published |
20100074577 | Hybrid optical switch apparatus - The invention relates to a hybrid optical switch, which is composed of a silicon micro-mirror-array and a mini-actuator array mainly. The invention which combines microelectromechanical systems technology and traditional precision machining technology, possesses the advantages of low cost, high accuracy, high fabrication yield, low actuation voltage, low power consumption, self-aligned micro-mirrors, and easy fiber alignment. | 03-25-2010 |
20110102875 | OPTICAL SWITCH AND OPTICAL SWITCH DEVICE HAVING THE SAME - Provided is an optical switch member including a bi-stable mechanism, and first and second electro-thermal actuators. The bi-stable mechanism includes a curved-beam disposed on a bending portion of a first cantilever, one end of the first cantilever having a driven portion disposed thereon. The first electro-thermal actuator includes a first beam of a first driven arm disposed on the bending portion. The second electro-thermal actuator includes a second beam of a second driven arm disposed on the bending portion. The ends of the first and second driven arms are adjacent to first and second sides of the driven arm, respectively. Also proposed is an optical switch device including a substrate, a third thermal actuator, and the optical switch member disposed on the substrate to form an optical switch device to thereby integrate the optical switch with variable optical attenuators on the substrate. | 05-05-2011 |