Patent application number | Description | Published |
20090067463 | STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME - A semiconductor substrate containing a single crystalline group IV semiconductor is provided. A single crystalline lattice mismatched group IV semiconductor alloy layer is epitaxially grown on a portion of the semiconductor layer, while another portion of the semiconductor layer is masked. The composition of the lattice mismatched group IV semiconductor alloy layer is tuned to substantially match the lattice constant of a single crystalline compound semiconductor layer, which is subsequently epitaxially grown on the single crystalline lattice mismatched group IV semiconductor alloy layer. Thus, a structure having both the group IV semiconductor layer and the single crystalline compound semiconductor layer is provided on the same semiconductor substrate. Group IV semiconductor devices, such as silicon devices, and compound semiconductor devices, such as GaAs devices having a laser emitting capability, may be formed on the on the same lithographic level of the semiconductor substrate. | 03-12-2009 |
20090298269 | STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME - A semiconductor substrate containing a single crystalline group IV semiconductor is provided. A single crystalline lattice mismatched group IV semiconductor alloy layer is epitaxially grown on a portion of the semiconductor layer, while another portion of the semiconductor layer is masked. The composition of the lattice mismatched group IV semiconductor alloy layer is tuned to substantially match the lattice constant of a single crystalline compound semiconductor layer, which is subsequently epitaxially grown on the single crystalline lattice mismatched group IV semiconductor alloy layer. Thus, a structure having both the group IV semiconductor layer and the single crystalline compound semiconductor layer is provided on the same semiconductor substrate. Group IV semiconductor devices, such as silicon devices, and compound semiconductor devices, such as GaAs devices having a laser emitting capability, may be formed on the on the same lithographic level of the semiconductor substrate. | 12-03-2009 |
20100252814 | SEMICONDUCTOR NANOWIRES HAVING MOBILITY-OPTIMIZED ORIENTATIONS - Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning. | 10-07-2010 |
20110026879 | FABRICATION-TOLERANT WAVEGUIDES AND RESONATORS - An optical waveguide having a core region with a substantially rectangular cross-section with a selected aspect ratio of width to height. Embodiments include devices incorporating the optical waveguide and methods for using the optical waveguide. | 02-03-2011 |
20110175063 | SEMICONDUCTOR NANOWIRES HAVING MOBILITY-OPTIMIZED ORIENTATIONS - Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning. | 07-21-2011 |
20110235390 | HIGH DENSITY MEMORY DEVICE - A memory device and a method of forming the same are provided. The memory device includes a substrate; a set of electrodes disposed on the substrate; a dielectric layer formed between the set of electrodes; and a transition metal oxide layer formed between the set of electrodes, the transition metal oxide layer configured to undergo a metal-insulator transition (MIT) to perform a read or write operation. | 09-29-2011 |
20120300534 | HIGH DENSITY MEMORY DEVICE - A method of operating a memory device having a dielectric material layer, a transition metal oxide layer and a set of electrodes each formed over a substrate, includes applying a voltage across the set of electrodes producing an electric field across the transition metal oxide layer enabling the transition metal oxide layer to undergo a metal-insulation transition (MIT) to perform a read or write operation on memory device. | 11-29-2012 |
Patent application number | Description | Published |
20100295020 | Method For Forming A Robust Top-Down Silicon Nanowire Structure Using A Conformal Nitride And Such Structure - A nanowire product and process for fabricating it has a wafer with a buried oxide (BOX) upper layer in which a well is formed and the ends of a nanowire are on the BOX layer forming a beam that spans the well. A mask coating is formed on the upper surface of the BOX layer leaving an uncoated window over a center part of the beam and also forming a mask coating around the beam intermediate ends between each end of the beam center part and a side wall of the well. Applying oxygen through the window thins the beam center part while leaving the wire intermediate ends over the well thicker and having a generally arched shape. A thermal oxide coating can be placed on the wire and also the mask on the BOX layer before oxidation. | 11-25-2010 |
20110107841 | PIEZORESISTIVE STRAIN SENSOR BASED NANOWIRE MECHANICAL OSCILLATOR - An apparatus is provided and includes compressed conductive elements that each have independently adjustable dimensions sufficient to provide substantially enhanced piezoresistance to a current flowing across each conductive element with each of the conductive elements subjected to compressive strain, the conductive elements being oscillated in a direction parallel to that of the compressive strain at a defined frequency such that a resistance of the conductive elements to the current is thereby substantially reduced. | 05-12-2011 |
20110207335 | Constrained Oxidation of Suspended Micro- and Nano-Structures - Techniques for preventing bending/buckling of suspended micro/nanostructures during oxidation are provided. In one aspect, a method for oxidizing a structure is provided. The method includes providing the structure having at least one suspended element selected from the group consisting of: a microstructure, a nanostructure and a combination thereof; surrounding the at least one suspended element in a cladding material; and oxidizing the at least one suspended element through the cladding material, wherein the cladding material physically constrains and thereby prevents distortion of the at least one suspended element during the oxidation. | 08-25-2011 |
20120280203 | TRANSPARENT PHOTODETECTOR - A transparent photodetector. The transparent photodetector includes a substrate; a waveguide on the substrate; a displaceable structure that can be displaced with respect to the substrate, the displaceable structure in proximity to the waveguide; and a silicon nanowire array suspended with respect to the substrate and mechanically linked to the displaceable structure, the silicon nanowire array comprising a plurality of silicon nanowires having piezoresistance. In operation, a light source propagating through the waveguide results in an optical force on the displaceable structure which further results in a strain on the nanowires to cause,a change in electrical resistance of the nanowires. The substrate may be a semiconductor on insulator substrate. | 11-08-2012 |
20130156365 | Fiber to Wafer Interface - An interface device includes a body portion having a single-mode waveguide portion including a substantially optically transparent material, a cladding portion defined by channels contacting the waveguide portion, the cladding portion including a substantially optically transparent polymer material, an engagement feature operative to engage a portion of a wafer, and a guide portion operative to engage a portion of an optical fiber ferrule. | 06-20-2013 |
20130251304 | FLEXIBLE FIBER TO WAFER INTERFACE - An interface device includes a flexible substrate portion, a flexible cladding portion arranged on the substrate portion, a flexible single-mode waveguide portion arranged on the cladding portion including a substantially optically transparent material, a first engagement feature operative to engage a portion of a wafer, and a connector portion engaging a first distal end of the flexible substrate portion, the connector portion operative to engage a portion of an optical fiber ferrule. | 09-26-2013 |
20130251305 | FLEXIBLE FIBER TO WAFER INTERFACE - A fiber to wafer interface system includes an interface device comprising a flexible substrate portion, a flexible cladding portion arranged on the substrate portion, a flexible single-mode waveguide portion arranged on the cladding portion including a substantially optically transparent material, a connector portion engaging a first distal end of the flexible substrate portion, the connector portion operative to engage a portion of an optical fiber ferrule, a wafer portion comprising a single mode waveguide portion arranged on a portion of the wafer, an adhesive disposed between a portion of the single mode waveguide portion of the body portion and the single mode waveguide portion of the wafer portion, the adhesive securing the body portion to the wafer portion. | 09-26-2013 |
20130283584 | Assembly of Electronic and Optical Devices - An assembly tool apparatus includes a manipulator having a range of motion defined by a plane and an axis that is substantially normal to the plane, a jig having an assembly surface operative to move from a first orientation relative to the axis to a second orientation relative to the axis, a first tool tip operative to engage with and be positioned by the manipulator, and a second tool tip operative to engage with and be positioned by the manipulator. | 10-31-2013 |
20130283591 | Assembly of Electronic and Optical Devices - A method for operating an assembly tool includes deposing a first component on an assembly surface with a first tool tip of a manipulator having a range of motion defined by a plane and an axis that is substantially normal to the plane, deposing a second component on the assembly surface, changing an orientation of the assembly surface relative to the axis from a first orientation to a second orientation, lifting the first component from the assembly surface with a second tool tip of the manipulator, and deposing the first component on the second component. | 10-31-2013 |
20140091374 | STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device. | 04-03-2014 |
20140151894 | FAR BACK END OF THE LINE STACK ENCAPSULATION - A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack. | 06-05-2014 |
20140151898 | FAR BACK END OF THE LINE STACK ENCAPSULATION - A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack. | 06-05-2014 |
20140177222 | SEMICONDUCTOR PHOTONIC PACKAGE - A method for assembling a semiconductor photonic package device includes bonding a portion of a first surface of a semiconductor die portion to a portion of a carrier portion, bonding a single mode optical ferrule portion to a portion of the first surface of the semiconductor die portion, and disposing a cover plate assembly in contact with the optical ferrule portion and the carrier portion. | 06-26-2014 |
20140179034 | SEMICONDUCTOR PHOTONIC PACKAGE - A method for assembling a semiconductor photonic package device includes bonding a portion of a first surface of a semiconductor die portion to a portion of a carrier portion, bonding a single mode optical ferrule portion to a portion of the first surface of the semiconductor die portion, and disposing a cover plate assembly in contact with the optical ferrule portion and the carrier portion. | 06-26-2014 |
20140201971 | ASSEMBLY OF ELECTRONIC AND OPTICAL DEVICES - A method for operating an assembly tool includes deposing a first component on an assembly surface with a first tool tip of a manipulator having a range of motion defined by a plane and an axis that is substantially normal to the plane, deposing a second component on the assembly surface, changing an orientation of the assembly surface relative to the axis from a first orientation to a second orientation, lifting the first component from the assembly surface with a second tool tip of the manipulator, and deposing the first component on the second component. | 07-24-2014 |
20140217485 | STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device. | 08-07-2014 |
20140270622 | MATERIAL STRUCTURES FOR FRONT-END OF THE LINE INTEGRATION OF OPTICAL POLARIZATION SPLITTERS AND ROTATORS - A polarization splitter and rotator of a wafer chip, an opto-electronic device and method of use is disclosed. The first waveguide of the wafer chip is configured to receive an optical signal from an optical device and propagate a transverse electric eigenstate of the received optical signal. The second waveguide is configured to receive a transverse magnetic eigenstate of the received optical signal from the first waveguide. The second waveguide includes a splitter end, a middle section and a rotator end, wherein the splitter end includes a layer of polycrystalline silicon, a layer of silicon oxide and a layer of silicon nitride, the rotated end includes a layer single crystal silicon, a layer silicon oxide and a layer of silicon nitride, and the middle section includes layers of single crystal silicon, silicon oxide polycrystalline silicon and silicon nitride. | 09-18-2014 |
20140270628 | MATERIAL STRUCTURES FOR FRONT-END OF THE LINE INTEGRATION OF OPTICAL POLARIZATION SPLITTERS AND ROTATORS - A polarization splitter and rotator of a wafer chip, an opto-electronic device and method of use is disclosed. The first waveguide of the wafer chip is configured to receive an optical signal from an optical device and propagate a transverse electric eigenstate of the received optical signal. The second waveguide is configured to receive a transverse magnetic eigenstate of the received optical signal from the first waveguide. The second waveguide includes a splitter end, a middle section and a rotator end, wherein the splitter end includes a layer of polycrystalline silicon, a layer of silicon oxide and a layer of silicon nitride, the rotated end includes a layer single crystal silicon, a layer silicon oxide and a layer of silicon nitride, and the middle section includes layers of single crystal silicon, silicon oxide polycrystalline silicon and silicon nitride. | 09-18-2014 |
20140270652 | FIBER PIGTAIL WITH INTEGRATED LID - A mechanism is provided for a fiber pigtail. The fiber pigtail includes a single mode fiber optic ribbon having a section of polymer ribbon removed to expose bare fibers, a fiber optic ferrule in contact with the single mode fiber optic ribbon at one distal end, and an integrated polymer lid permanently attached to the bare fibers of the single mode fiber optic ribbon at another distal end of the single mode fiber optic ribbon. | 09-18-2014 |
20150177466 | FIBER PIGTAIL WITH INTEGRATED LID - A mechanism is provided for a fiber pigtail. The fiber pigtail includes a single mode fiber optic ribbon having a section of polymer ribbon removed to expose bare fibers, a fiber optic ferrule in contact with the single mode fiber optic ribbon at one distal end, and an integrated polymer lid permanently attached to the bare fibers of the single mode fiber optic ribbon at another distal end of the single mode fiber optic ribbon. | 06-25-2015 |
20160091675 | CONNECTOR FOR WAVEGUIDE AND ALIGNMENT METHOD - Various embodiments are directed to a connector for coupling optical signals to a semiconductor device. In one embodiment, the connector includes a connector member having a recessed portion to arrange a plurality of waveguides formed side-by-side in a transverse direction. A backup member is arranged within the recessed portion interposing the plurality of waveguides between the connector member and the backup member. The recessed portion includes a plurality of ridges arranged in a staggered pattern relative to the plurality of waveguides for positioning the plurality of waveguides relative to the connector. | 03-31-2016 |