Patent application number | Description | Published |
20090067277 | Memory device command decoding system and memory device and processor-based system using same - Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode. | 03-12-2009 |
20090154228 | Random Access Memory Employing Read Before Write for Resistance Stabilization - An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase change material in the cells. When an attempt is made during a write command to write a data state to a bit which already has that data state, such matching data states are identified and writing to those bits is precluded during the write command. In one embodiment, both the incoming data to be written to a bit and the data currently present at that bit address are latched. These latched data are then compared (e.g., with an XOR gate) to determine which bits have a matching data state. The results of this comparison are used as an enable signal to the write (column) driver in the PCRAM memory array, with the effect that only data bits having different data state are written, while data bits having a matching data state are not needlessly re-written. Because matching data states are ignored, reliability problems associated with such redundant writing are alleviated, and power is saved. | 06-18-2009 |
20090268544 | MEMORY DEVICE AND METHOD HAVING PROGRAMMABLE ADDRESS CONFIGURATIONS - A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously applied to the address bus terminals in the first and second sets, and they are simultaneously stored in respective address registers. In a second addressing configuration, a plurality of sets of address signals are sequentially applied to the address bus terminals in only the first set of address bus terminals. Each set of address signals is then stored in a different address register. | 10-29-2009 |
20100174887 | Buses for Pattern-Recognition Processors - Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively. | 07-08-2010 |
20100174929 | Method and Systems for Power Consumption Management of a Pattern-Recognition Processor - Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. In some embodiments, the pattern-recognition processor includes a first block of feature cells coupled to a decoder via a first plurality of local input conductors, a first block-disabling circuit, and a plurality of global input conductors. The pattern-recognition processor further includes a second block of feature cells coupled to the decoder via a second plurality of local input conductors, a second block-disabling circuit, and the plurality of global input conductors. | 07-08-2010 |
20100175130 | Pattern-Recognition Processor with Matching-Data Reporting Module - Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a matching-data reporting module, which may have a buffer and a match event table. The buffer may be coupled to a data stream and configured to store at least part of the data stream, and the match event table may be configured to store data indicative of a buffer location corresponding with a start of a search criterion being satisfied. | 07-08-2010 |
20100214864 | MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode. | 08-26-2010 |
20110047311 | MULTI-PORT MEMORY AND OPERATION - Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications. | 02-24-2011 |
20110093662 | MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY - Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s). | 04-21-2011 |
20110093665 | MEMORY HAVING INTERNAL PROCESSORS AND METHODS OF CONTROLLING MEMORY ACCESS - Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed. | 04-21-2011 |
20110138251 | MEMORY SYSTEM AND METHOD USING PARTIAL ECC TO ACHIEVE LOW POWER REFRESH AND FAST ACCESS TO DATA - A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells. | 06-09-2011 |
20110138252 | MEMORY SYSTEM AND METHOD USING ECC WITH FLAG BIT TO IDENTIFY MODIFIED DATA - A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data. | 06-09-2011 |
20110167237 | MULTI-BANK MEMORY ACCESSES USING POSTED WRITES - Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access. | 07-07-2011 |
20120198194 | Multi-Bank Memory Accesses Using Posted Writes - Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access. | 08-02-2012 |
20120266005 | METHOD AND DEVICE TO REDUCE POWER CONSUMPTION OF A PATTERN-RECOGNITION PROCESSOR - A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis. The pattern recognition processor also includes block deactivation logic configured to dynamically power-down the block. | 10-18-2012 |
20130139029 | MEMORY SYSTEM AND METHOD USING PARTIAL ECC TO ACHIEVE LOW POWER REFRESH AND FAST ACCESS TO DATA - A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells. | 05-30-2013 |
20130254626 | MEMORY SYSTEM AND METHOD USING ECC WITH FLAG BIT TO IDENTIFY MODIFIED DATA - A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device, The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data. | 09-26-2013 |
20140047305 | MEMORY SYSTEM AND METHOD USING ECC WITH FLAG BIT TO IDENTIFY MODIFIED DATA - A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data. | 02-13-2014 |
20140156948 | APPARATUSES AND METHODS FOR PRE-FETCHING AND WRITE-BACK FOR A SEGMENTED CACHE MEMORY - Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. Additional information is read from memory based on the transaction history, wherein the requested information and the additional information are read together from memory. The requested information is cached in a segment of a cache line of the cache block and the additional information in cached another segment of the cache line. In another example, the transaction history is also updated to reflect the caching of the requested information and the additional information. In another example, read masks associated with the cache tag are referenced for the transaction history, the read masks identifying segments of a cache line previously accessed. | 06-05-2014 |
20140244564 | PATTERN-RECOGNITION PROCESSOR WITH MATCHING-DATA REPORTING MODULE - Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a matching-data reporting module, which may have a buffer and a match event table. The buffer may be coupled to a data stream and configured to store at least part of the data stream, and the match event table may be configured to store data indicative of a buffer location corresponding with a start of a search criterion being satisfied. | 08-28-2014 |
20140244948 | MEMORY HAVING INTERNAL PROCESSORS AND METHODS OF CONTROLLING MEMORY ACCESS - Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed. | 08-28-2014 |
20140281149 | APPARATUSES AND METHODS FOR ADAPTIVE CONTROL OF MEMORY - Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data. | 09-18-2014 |
20140289482 | MULTI-PORT MEMORY AND OPERATION - Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications. | 09-25-2014 |
20140359391 | MEMORY SYSTEM AND METHOD USING PARTIAL ECC TO ACHIEVE LOW POWER REFRESH AND FAST ACCESS TO DATA - A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells. | 12-04-2014 |