Patent application number | Description | Published |
20080237854 | METHOD FOR FORMING CONTACT PADS - First, a substrate having a conductor therein is provided. Next, a first dielectric layer is disposed on the conductor and the substrate and a first opening is formed in the first dielectric layer for exposing the conductor. A first metal layer is deposited over the surface of the first dielectric layer and into the first opening. Next, an etching stop layer and a second metal layer are deposited over the surface of the first metal layer, and a pattern transfer process is performed by using a second dielectric layer as a mask to remove a portion of the first metal layer, the etching stop layer, and the second metal layer for exposing the first dielectric layer. A passivation layer is disposed on the second metal layer and the first dielectric layer and a second opening is formed in the passivation layer to expose a portion of the second metal layer. | 10-02-2008 |
20080246144 | METHOD FOR FABRICATING CONTACT PADS - A method for fabricating a contact pad is disclosed. A first metal layer is disposed on a substrate for serving as a probing region. A second metal layer is disposed on the substrate thereafter to serve as an electrical connection region. Preferably, the first metal layer and the second metal layer are composed of different material and are electrically connected. The present invention uses two different metals to form a probing region and an electrical connection region of a contact pad. The probing region is used for providing a contacting surface for a test probe, whereas the electrical connection region is used for establishing an electrical connection in the later bumping or wire bonding process. By providing a contact pad having two different regions, the present invention is able to achieve probing process while prevent the surface of the contact pad from being damaged by the contact of test probes. | 10-09-2008 |
20090033346 | GROUP PROBING OVER ACTIVE AREA PADS ARRANGEMENT - A group probing over active area (POAA) pads arrangement includes a chip having a set of bonding pads, at least a first set of probing pads and a second set of probing pads. Each of the first set of probing pads and the second set of probing pads are electrically connected to one of the corresponding bonding pads, respectively. And each of the first set of probing pads and the second set of probing pads are interlaced in a diagonal line pattern. According to a concept of grouping and interlacing the probing pads, each bonding pad obtains at least two probing pads. Therefore times of test probing performed on each probing pad are reduced and repeated probe's pressures toward inter metal dielectric (IMD) layers underneath the probing pads are consequently reduced. | 02-05-2009 |
20090283869 | Scribe line structure for wafer dicing and method of making the same - The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer. | 11-19-2009 |
20100289021 | SCRIBE LINE STRUCTURE AND METHOD FOR DICING A WAFER - A scribe line structure is disclosed. The scribe line structure includes a semiconductor substrate having a die region, a die seal ring region, disposed outside the die region, a scribe line region disposed outside the die seal ring region and a dicing path formed on the scribe line region. Preferably, the center line of the dicing path is shifted away from the center line of the scribe line region along a first direction. | 11-18-2010 |
Patent application number | Description | Published |
20090094414 | Firmware Update for Storage Device - A storage device includes a firmware memory, a buffer memory, a processor and a memory update controller. When the storage device is under a normal mode, the memory update controller is in an idle state. The processor controls the storage device to fetch an update firmware and store the update firmware into the buffer memory. When the storage device is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code. | 04-09-2009 |
20100097909 | METHOD AND APPARATUS FOR DETECTING SPECIFIC SIGNAL PATTERN IN A SIGNAL READ FROM AN OPTICAL DISC - A signal pattern detecting apparatus, which is capable of detecting a physical mark in a read back signal being read from an optical disc, includes a matching signal generator, a signal comparing device, and a decision circuit. The matching signal generator is utilized for generating a matching signal, capable of being utilized to identify the physical mark, according to a reference clock and a wobble clock. The signal comparing device is electrically connected to the matching signal generator, and utilized for comparing the matching signal with a wobble data signal to generate a comparison signal. The decision circuit is electrically connected to the signal comparing device, and utilized for generating an indication signal according to the comparison signal and a threshold value. Both the wobble data signal and the wobble clock are derived from the read back signal. | 04-22-2010 |