Patent application number | Description | Published |
20090116309 | SEMICONDUCTOR DEVICE - A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD | 05-07-2009 |
20090180343 | SEMICONDUCTOR MEMORY DEVICE - A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation. | 07-16-2009 |
20110103136 | SEMICONDUCTOR MEMORY DEVICE - A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation. | 05-05-2011 |
Patent application number | Description | Published |
20080239865 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature. | 10-02-2008 |
20090066390 | TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - Disclosed is a timing control circuit which receives a first clock having a period T | 03-12-2009 |
20090102524 | TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal. | 04-23-2009 |
20100109756 | SEMICONDUCTOR DEVICE - A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip. | 05-06-2010 |
20110079858 | SEMICONDUCTOR MEMORY DEVICE HAVING A SENSE AMPLIFIER CIRCUIT WITH DECREASED OFFSET - A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit. | 04-07-2011 |
Patent application number | Description | Published |
20080201051 | Vehicle driving force control device - A driving force control device includes an individual-wheel friction-circle limit-value calculating portion that calculates friction-circle limit-values of individual wheels, an individual-wheel requested-resultant-tire-force calculating portion that calculates requested resultant tire forces of the individual wheels, an individual-wheel resultant-tire-force calculating portion that calculates resultant tire forces of the individual wheels, an individual-wheel requested-excessive-tire-force calculating portion that calculates requested excessive tire forces of the individual wheels, an individual-wheel excessive-tire-force calculating portion that calculates excessive tire forces of the individual wheels, an excessive-tire-force calculating portion that calculates an excessive tire force, an over-torque calculating portion that calculates an over-torque, and a control-amount calculating portion that calculates a control amount that is output to an engine control unit. | 08-21-2008 |
20110109784 | IMAGING APPARATUS - An imaging apparatus includes a display unit capable of being displaced between a non use state and a use state in such a manner that a display surface displaying an image of a subject is directed at least to the subject or a user in the use state, and a display control unit that inverts a direction in a vertical direction of the image of the subject displayed on the display surface in response to an operation on an operation member when the display unit is in the use state and cancels the inversion when the display unit is in the non use state. | 05-12-2011 |
20110134678 | Semiconductor device having hierarchical structured bit line - A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained. | 06-09-2011 |
20110172883 | STEERING CONTROL SYSTEM FOR VEHICLE - A steering control section has a first steering angle correction amount calculating section, a second steering angle correction amount calculating section, and a motor rotational angle calculating section. The first correction amount calculating section calculates a first correction amount based on a vehicle speed and an actual steering wheel angle. The second correction amount calculating section calculates a second correction amount through multiplying a control gain corresponding to the vehicle speed with a value calculated by low-pass filtering a differential value of steering wheel angle. The motor rotational angle calculating section calculates a motor rotational angle corresponding to the value adding the first and second steering angle correction amount, and outputs it to a motor driving section so as to drive an electric motor for correcting the steering angle. Thereby, an unstable vehicle behavior due to a resonance of a yaw motion caused in the steering operation can be suppressed. | 07-14-2011 |
20110205820 | Semiconductor device - The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal. | 08-25-2011 |
20120147244 | IMAGE PICKUP APPARATUS - An image pickup apparatus capable of giving a shooter the same rotary operation feeling regardless of the rotating direction, and displaying an erect image to a shooter at all times. A two-axis hinge is provided with a first bearing that supports a display unit rotatably in right and left directions and a second bearing that supports the display unit in rotated states rotatably so as to direct the screen to front and rear sides. A first axial rotation detector detects the rotation of the display unit by the first bearing. A second axial rotation detector detects the rotation of the display unit in the rotated states by the second bearing to direct the screen to the front and rear sides. A control unit switches display orientation of an image displayed on the display unit based on detection results from the first and second axial rotation detectors. | 06-14-2012 |
20130107101 | IMAGE DISPLAY DEVICE WITH OPERATION UNIT EXCELLENT IN OPERABILITY AND IMAGE PICKUP APPARATUS HAVING THE SAME | 05-02-2013 |
20140003116 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL STRUCTURED BIT LINES | 01-02-2014 |
20140231829 | SEMICONDUCTOR DEVICE - Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP | 08-21-2014 |