Pontius, US
Dale E. Pontius, Colchester, VT US
Patent application number | Description | Published |
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20110170368 | CHARGE PUMP SYSTEM AND METHOD UTILIZING ADJUSTABLE OUTPUT CHARGE AND COMPILATION SYSTEM AND METHOD FOR USE BY THE CHARGE PUMP - Charge pump circuit includes a plurality of boost capacitors. An output charge of the charge pump circuit is adjusted by selecting a number of the boost capacitors at least one of using a digital control word and programming of a wiring level. A method of boosting supply voltage uses a charge pump circuit. The method includes adjusting an output charge of the charge pump circuit by selecting a number of boost capacitors at least one of using a digital control word and by programming of a wiring level | 07-14-2011 |
Jeffrey Pontius US
Patent application number | Description | Published |
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20090065958 | EVAPORATIVE HUMIDIFIER PAD MADE OF RIGIDIFYING LAYER LAMINATED TO PAPER LAYER AND METHOD OF CONSTRUCTING - A humidifier pad made of a plurality of laminated sheets connected together in a stack. Each of the sheets is made of a two layer laminate material made of a first layer of a rigidifying material, such as aluminum, and a second layer made of an absorbent layer, such as paper. The layers of each of the sheets are first laminated together, and then each sheet is slit and expanded in a conventional manner. Subsequently, each sheet is bonded to a next adjacent sheet to form a pad. | 03-12-2009 |
Karen Y. Pontius, Aromas, CA US
Patent application number | Description | Published |
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20100081653 | 2-[1H-Benzimidazol-2(3H)-ylidene]-2-(pyrimidin-2-yl)acetamides and 2-[benzothiazol-2(3H)-ylidene]-2-(pyrimidin-2-yl)acetamides as kinase inhibitors - 2-[1H-benzimidazol-2(3H)-ylidene]-2-(pyrimidin-2-yl)acetamides and 2-[benzothiazol-2(3H)-ylidene]-2-(pyrimidin-2-yl)acetamides and their salts are kinase inhibitors, useful in the treatment of cancer. | 04-01-2010 |
Peter Y. Pontius, Waterloo, NY US
Tim Pontius, Crystal Lake, IL US
Patent application number | Description | Published |
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20080256377 | Power Management for Buses in Cmos Circuits - The invention relates to a controlled shut-down of an electronic circuit or circuits such that the electrical power consumption of that circuit or circuits is minimized and that each said circuit is at a status which is a pre-determined state ( | 10-16-2008 |
20080279224 | Alignment and Deskew For Multiple Lanes of Serical Interconnect - Methods and apparatus are provided for data communication between a transmitter and receiver over a plurality of serial links, which cause the transmitter to send serialized groups of bits down each lane, in such a way that the first bit of each group (each lane) is guaranteed to arrive in the correct order at the receiving end. Various embodiments of the present invention include declaring a budget for the maximum skew between lanes. In such embodiments, subsequent to determining the skew budget between lanes, the data to be transmitted is divided into groups of N bits, where N is any convenient number larger than M times S, with M being the number of lanes and S being the budgeted skew, in bit times. | 11-13-2008 |
20080279225 | Synchronized Receiver - There is provided a method of operating a communications system comprising a transmitting station and a receiving station, the method in the transmitting station comprising encoding a clock signal with data to form encoded signals for transmission; transmitting the encoded signals to the receiving station; the method in the receiving station comprising decoding the encoded signals to extract the clock signal and data; processing the data under the control of the decoded clock signal. The method further comprises, when no data is required to be transmitted to the receiving station, transmitting further encoded signals to the receiving station in order for the receiving station to decode the further encoded signals and extract a clock signal. | 11-13-2008 |
20100061428 | SPACED ONE-HOT RECEIVER - A mobile device that incorporates the MIPI D-PHY specification has data lanes for carrying data between electronic modules within the device. The data lanes may incorporate a spaced-one-hot approach for asynchronously receiving a data signal over a two-wire interface. A two-wire receive interface is provided that uses an exclusive-NOR to capture a timing signal along with a set-reset flip-flop which holds the state of the data line so that a D flip-flop that is clocked on the falling edge of the timing signal received from the exclusive-NOR gate can sample the data and provide an accurate asynchronous data output. | 03-11-2010 |
Timothy A. Pontius, Crystal Lake, IL US
Patent application number | Description | Published |
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20080270875 | Two-Phase Data-Transfer Protocol - A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module used to determine availability of data on the first data bus in response to the first data integrity-indicating signal. | 10-30-2008 |
20150026494 | INTELLIGENT MESOCHRONOUS SYNCHRONIZER - A method and apparatus for transmitting data over a clock-gated mesochronous clock domain boundary in an interconnect network of an integrated circuit. New data is received into storage buffers within a sender domain. The data is synchronized by sending time-controlled signals from storage elements in a sender control within the sender domain to corresponding inputs in a receiver control signal path in a receiver domain. Multiplexers are signaled to sequentially transmit the data from the storage buffers across the domain boundary to the receiver domain according to the time-controlled signals received from the sender control by the receiver control signal path, where the multiplexers receive signals from a data path pointer counter in communication with the receiver control signal path. | 01-22-2015 |
Timothy Allen Pontius, Crystal Lake, IL US
Patent application number | Description | Published |
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20100174521 | DATA PROCESSING WITH CIRCUIT MODELING - Various aspects of the present invention are directed to design modeling and/or processing of streaming data. According to an example embodiment, a system to model a hardware specification includes a platform ( | 07-08-2010 |
20110050313 | METHODS AND SYSTEMS RELATED TO A CONFIGURABLE DELAY COUNTER USED WITH VARIABLE FREQUENCY CLOCKS - In certain arrangements and methods, a reset-able counter ( | 03-03-2011 |