Patent application number | Description | Published |
20090065925 | DUAL-SIDED CHIP ATTACHED MODULES - An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate. | 03-12-2009 |
20100263913 | METAL WIRING STRUCTURES FOR UNIFORM CURRENT DENSITY IN C4 BALLS - In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure abutting the metal pad, a lower level metal line structure located underneath the upper level metal line structure, and a set of metal vias that provide electrical connection between the lower level metal line structure located underneath the upper level metal line structure. In another embodiment, the reliability of a C4 ball is enhanced by employing a metal pad structure having a set of integrated metal vias that are segmented and distributed to facilitate uniform current density distribution within the C4 ball. The area | 10-21-2010 |
20120080797 | METAL WIRING STRUCTURES FOR UNIFORM CURRENT DENSITY IN C4 BALLS - In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure abutting the metal pad, a lower level metal line structure located underneath the upper level metal line structure, and a set of metal vias that provide electrical connection between the lower level metal line structure located underneath the upper level metal line structure. In another embodiment, the reliability of a C4 ball is enhanced by employing a metal pad structure having a set of integrated metal vias that are segmented and distributed to facilitate uniform current density distribution within the C4 ball. The areal density of the cross-sectional area in the plurality of metal vias is higher at the center portion of the metal pad than at the peripheral portion of the planar portion of the metal pad. | 04-05-2012 |
Patent application number | Description | Published |
20110161682 | PROCESSOR VOLTAGE REGULATION - A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor. | 06-30-2011 |
20110169131 | DEEP TRENCH DECOUPLING CAPACITOR - Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer. | 07-14-2011 |
20120181700 | INTEGRATED CIRCUIT AND DESIGN STRUCTURE HAVING REDUCED THROUGH SILICON VIA-INDUCED STRESS - Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate. | 07-19-2012 |
20130147015 | DEEP TRENCH DECOUPLING CAPACITOR AND METHODS OF FORMING - Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer. | 06-13-2013 |
20140209908 | FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING - Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly. | 07-31-2014 |
Patent application number | Description | Published |
20110037161 | ELECTROSTATIC CHUCKING OF AN INSULATOR HANDLE SUBSTRATE - A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip. | 02-17-2011 |
20110057319 | ARRANGING THROUGH SILICON VIAS IN IC LAYOUT - A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage. | 03-10-2011 |
20110108948 | INTEGRATED DECOUPLING CAPACITOR EMPLOYING CONDUCTIVE THROUGH-SUBSTRATE VIAS - A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips. | 05-12-2011 |
20110180896 | METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS - A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided. | 07-28-2011 |
Patent application number | Description | Published |
20140032329 | SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR GENERATING A FEED MESSAGE - An apparatus, method, and computer readable storage medium for generating a feed message and receiving information related thereto. At least one request to generate a feed message is received from an external party system, and includes message content and one or more sets of instructions provided by the external party system. The feed message is generated in accordance with the at least one request and stored. The feed message is also transmitted to a mobile device. One or more message acknowledgments are received from the mobile device, including any one of: a receiving message acknowledgment, a viewed message acknowledgment, and an operated message acknowledgment, or a combination thereof. A message state database is updated in accordance with the one or more message acknowledgments received from the mobile device. | 01-30-2014 |
20140032709 | SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR RECEIVING A FEED MESSAGE - An apparatus, method, and computer readable storage medium for receiving a feed message from an external party system. The feed message is received from an external party system, and includes message content, which may be text, images, or a combination thereof, and one or more sets of instructions. The message content can be displayed on a display which can receive one or more commands. A plurality of message acknowledgments can also be generated, including any one of: a received message acknowledgment when the feed message is received, a viewed message acknowledgment when the message content is displayed, and an operated message acknowledgment when the one or more sets of instructions are executed, or a combination thereof. The plurality of message acknowledgments can be stored in a memory, and transmitted to a remote server. | 01-30-2014 |
20140074581 | SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR MANAGING SERVICE PROVIDER LOYALTY PROGRAMS - Methods, systems and computer program products are provided for managing service provider loyalty programs. Loyalty program information associated with a service provider is generated. The loyalty program information defines a loyalty program. An electronic loyalty card based on the loyalty program is stored at the mobile device after enrollment of the mobile device. The loyalty program information associated with the loyalty card is enabled to be redeemed at a transaction location, and the loyalty program information is reconciled between the service provider and the mobile device. | 03-13-2014 |
20140074616 | SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR MANAGING SERVICE PROVIDER OFFERS - Methods, systems and computer program products are provided for managing service provider offers. An offer associated with a service provider is generated and the offer includes attributes defining the offer. A campaign is selected to pair the offer to. The campaign includes criteria for receiving the offer. The offer is delivered to a mobile device associated with a consumer matching the campaign criteria, and is rendered at the mobile device. | 03-13-2014 |