Patent application number | Description | Published |
20080305636 | METHOD OF FORMING FINE PATTERN EMPLOYING SELF-ALIGNED DOUBLE PATTERNING - There are provided a method of forming a fine pattern employing self-aligned double patterning. The method includes providing a substrate. First mask patterns are formed on the substrate. A reactive layer is formed on the substrate having the first mask patterns. The reactive layer adjacent to the first mask patterns is reacted using a chemical attachment process, thereby forming sacrificial layers along outer walls of the first mask patterns. The reactive layer that is not reacted is removed to expose the sacrificial layers. Second mask patterns are formed between the sacrificial layers adjacent to sidewalls of the first mask patterns facing each other. The sacrificial layers are removed to expose the first and second mask patterns and the substrate exposed between the first and second mask patterns. The substrate is etched using the first and second mask patterns as an etching mask. | 12-11-2008 |
20080308875 | MASK ROM DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE MASK ROM DEVICE, AND METHODS OF FABRICATING MASK ROM DEVICE AND SEMICONDUCTOR DEVICE - A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity. | 12-18-2008 |
20090312413 | Composition Comprising Tanshinone Compounds Isolated From The Extract Of Salviae Miltiorrhizae Radix For Treating Or Preventing Cognitive Dysfunction And The Use Thereof - A composition comprising tanshinone compounds selected from the group consisting of miltirone, 1,2-didehydromiltirone, tanshinone IIA, tanshinone I and dihydrotanshinone I isolated from | 12-17-2009 |
20100197685 | NOVEL BENZOFURAN TYPE DERIVATIVES, A COMPOSITION COMPRISING THE SAME FOR TREATING OR PREVENTING COGNITIVE DYSFUNCTION AND THE USE THEREOF - The present invention relates to the novel benzofuran derivatives, the preparation thereof and the composition comprising the same. The benzofuran derivatives of the present invention showed potent inhibiting activity of beta-amyloid aggregation and cell cytotoxicity resulting in stimulating the proliferation of neuronal cells as well as recovering activity of memory learning injury caused by neuronal cell injury using transformed animal model with beta-amyloid precursor gene, therefore the compounds can be useful in treating or preventing cognitive function disorder. | 08-05-2010 |
20100285641 | MASK ROM DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE MASK ROM DEVICE, AND METHODS OF FABRICATING MASK ROM DEVICE AND SEMICONDUCTOR DEVICE - A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity. | 11-11-2010 |
20110055623 | SOLID STATE STORAGE SYSTEM WITH IMPROVED DATA MERGING EFFICIENCY AND CONTROL METHOD THEREOF - The presented solid state storage system provides an efficient manner of processing read and write operations in a memory block that has a faulty page of memory within it. The solid state storage system includes a flash memory area and a memory controller. The memory controller stores link information into a buffer, allocates a first temporary physical block to resume operations of the bad block past the first bad page, updates and stores mapping information associated with the remaining portions of the bad block past the first bad page, and merges together those valid pages from among the bad block into a final physical block by merging together all prior successfully operated valid pages from among the bad block with any subsequently successfully operated valid pages which are associated with successful operations subsequently to the failure in the first bad page of the bad block. | 03-03-2011 |
20110107016 | SOLID STATE STORAGE SYSTEMS AND METHODS FOR FLEXIBLY CONTROLLING WEAR LEVELING - Solid-state storage systems and methods are provided for controlling a wear leveling process for uniform use of the memory cells that replaces worn memory blocks with less frequently used memory blocks. The wear leveling process is performed by changing the physical locations of the storage cells within each memory zone or plane. Reference values of target memory block erase counts and worn memory block erase counts are used for searching target memory blocks to be used as replacements. | 05-05-2011 |
20120245165 | NOVEL BENZOFURAN TYPE DERIVATIVES, A COMPOSITION COMPRISING THE SAME FOR TREATING OR PREVENTING COGNITIVE DYSFUNCTION AND THE USE THEREOF - The present invention relates to the novel benzofuran derivatives, the preparation thereof and the composition comprising the same. The benzofuran derivatives of the present invention showed potent inhibiting activity of beta-amyloid aggregation and cell cytotoxicity resulting in stimulating the proliferation of neuronal cells as well as recovering activity of memory learning injury caused by neuronal cell injury using transformed animal model with beta-amyloid precursor gene, therefore the compounds can be useful in treating or preventing cognitive function disorder. | 09-27-2012 |
20120245225 | NOVEL BENZOFURAN TYPE DERIVATIVES, A COMPOSITION COMPRISING THE SAME FOR TREATING OR PREVENTING COGNITIVE DYSFUNCTION AND THE USE THEREOF - The present invention relates to the novel benzofuran derivatives, the preparation thereof and the composition comprising the same. The benzofuran derivatives of the present invention showed potent inhibiting activity of beta-amyloid aggregation and cell cytotoxicity resulting in stimulating the proliferation of neuronal cells as well as recovering activity of memory learning injury caused by neuronal cell injury using transformed animal model with beta-amyloid precursor gene, therefore the compounds can be useful in treating or preventing cognitive function disorder. | 09-27-2012 |
20120259006 | NOVEL BENZOFURAN TYPE DERIVATIVES, A COMPOSITION COMPRISING THE SAME FOR TREATING OR PREVENTING COGNITIVE DYSFUNCTION AND THE USE THEREOF - The present invention relates to the novel benzofuran derivatives, the preparation thereof and the composition comprising the same. The benzofuran derivatives of the present invention showed potent inhibiting activity of beta-amyloid aggregation and cell cytotoxicity resulting in stimulating the proliferation of neuronal cells as well as recovering activity of memory learning injury caused by neuronal cell injury using transformed animal model with beta-amyloid precursor gene, therefore the compounds can be useful in treating or preventing cognitive function disorder. | 10-11-2012 |
20140059501 | SCREEN DISPLAY CONTROL METHOD OF ELECTRONIC DEVICE AND APPARATUS THEREFOR - A method and apparatus for zooming in or out and displaying a screen according a gesture of a user is provided. The method includes sensing gesture input, determining whether the gesture input corresponds to a predetermined pattern of a first semicircle or semi oval shape, and zooming in or out the image displayed on the screen and displaying a zoomed in or zoomed out image on a screen wherein the zoom ratio is in proportion to a radius of a first semicircle or a radius of a long or short axis of a first semi oval when the gesture input is the pattern of the first semicircle or semi oval shape. | 02-27-2014 |
20140101386 | DATA STORAGE DEVICE INCLUDING BUFFER MEMORY - A data storage device includes a data storage medium a micro control unit (MCU) connected to a host through a first interface method and configured to control the data storage medium in response to a request of the host; and a buffer memory connected to the host through a second interface method, connected to the MCU, and controlled by the MCU and the host, respectively. | 04-10-2014 |
20150259646 | Methods for Isolating and Proliferating Autologous Cancer AntiGen-Specific CD8+ T Cells - Provided is a method for isolating and proliferating autologous cancer antigen-specific CD8 | 09-17-2015 |
Patent application number | Description | Published |
20120170320 | METHOD AND APPARATUS FOR GENERATING CURRENT COMMAND VALUE FOR TRACKING MAXIMUM POWER POINT IN SOLAR ENERGY GENERATING SYSTEM - There are provided a method and an apparatus for generating a current command value for tracking the maximum power point of a solar energy generating system. The apparatus includes: a voltage detector detecting a voltage input into the flyback power converter; a first calculator calculating an output power from the detected input voltage; a second calculator calculating a power variation based on the calculated output power and a voltage variation of the input voltage; and a current command value generator generating a current command value for tracking the maximum power point of the solar cell module from the calculated voltage variation and the calculated power variation. Accordingly, a current command value after calculating an output power may be generated with only a voltage detector, without a current detector, thereby reducing the costs of a solar energy generating system by decreasing the costs for a high-priced current detector, and simplifying circuit. | 07-05-2012 |
20120327558 | CONDUCTIVE PASTE COMPOSITION FOR INTERNAL ELECTRODE AND MULTILAYER CERAMIC CAPACITOR INCLUDING THE SAME - A conductive paste composition for an internal electrode, and a multilayer ceramic capacitor (MLCC) including the same are provided. The conductive paste composition for an internal electrode includes: 100 parts by weight of metal powder particles; and 0.1 to 10 parts by weight of carbon nano-tubes (CNTs). The conductive paste composition for an internal electrode may control sintering shrinkage of metal powder particles. | 12-27-2012 |
20130009515 | CONDUCTIVE PASTE COMPOSITION FOR INTERNAL ELECTRODES AND MULTILAYER CERAMIC ELECTRONIC COMPONENT INCLUDING THE SAME - There are provided a conductive paste composition for an internal electrode and a multilayer ceramic electronic component including the same. The conductive paste composition includes: 100 moles of a metal powder; 0.5 to 4.0 moles of a ceramic powder; and 0.03 to 0.1 mole of a silica (SiO | 01-10-2013 |
20130112338 | METHOD OF MANUFACTURING MULTILAYER CERAMIC CAPACITOR - There is provided a method of manufacturing a multilayer ceramic capacitor including: laminating ceramic green sheets having internal electrodes printed thereon to form a ceramic laminated body; cutting the ceramic laminated body; applying slurry including a ceramic powder to the ceramic laminated body; and drying the slurry applied to the ceramic laminated body. According to an embodiment of the present invention, cracks generated in a manufacturing process of the multilayer ceramic capacitor may be removed, such that the multilayer ceramic capacitor may have excellent reliability. | 05-09-2013 |
20130301184 | CONDUCTIVE PASTE COMPOSITION FOR INTERNAL ELECTRODE, MULTILAYER CERAMIC ELECTRONIC COMPONENT, AND METHOD OF MANUFACTURING THE SAME - There are provided a conductive paste composition for an internal electrode, a multilayer ceramic electronic component including the same, and a method of manufacturing the same, the conductive paste composition including: a metal powder; and an additive including at least one selected from glutamic acid, amino acids, thiols, and hydrocarbons. | 11-14-2013 |
20130321976 | NICKEL NANOPARTICLE, METHOD OF PREPARING THE SAME, AND MULTILAYER CERAMIC CAPACITOR USING THE SAME - There is provided a method of preparing a nickel nanoparticle, the method including: forming an aqueous solution by mixing water and a solution containing a hydroxyl group; forming a mixed liquid by adding carboxylic acid to the aqueous solution at a ratio of 10 to 20 wt % with regard to the solution containing a hydroxyl group; and adding a nickel salt to the mixed liquid and stirring the mixed liquid. | 12-05-2013 |
20140126109 | MULTILAYER CERAMIC ELECTRONIC COMPONENT AND FABRICATING METHOD THEREOF - There is provided a multilayered ceramic electronic component including: a ceramic body including dielectric layers; internal electrodes disposed to face each other, having the dielectric layers therebetween; and external electrodes formed on outer surfaces of the ceramic body and electrically connected to the internal electrodes, wherein the internal electrodes include a first ceramic powder formed of barium titanate (BaTiO | 05-08-2014 |
20140126111 | MULTILAYERED CERAMIC ELECTRONIC COMPONENT AND FABRICATING METHOD THEREOF - There is provided a multilayered ceramic electronic component including: a ceramic body including dielectric layers; internal electrodes disposed to face each other, having the dielectric layer therebetween; and external electrodes formed at an outer side of the ceramic body and respectively electrically connected to the internal electrodes, wherein the internal electrodes include a single ceramic layer therein. The disconnection generated by a difference in contraction and extension rates due to a difference in the sintering temperature between the internal electrodes and the dielectric is prevented and the electrode connectivity and the coverage are maintained, whereby the high capacitance multilayered ceramic electronic component having excellent reliability may be implemented. | 05-08-2014 |
20140177133 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - There is provided a multilayer ceramic electronic component, including: a ceramic body including dielectric layer; and first and second internal electrodes formed inside the ceramic body and disposed to face each other with the dielectric layer interposed therebetween, wherein, on a cross section of the ceramic body taken in length-thickness (L-T) directions thereof, a secondary phase material is formed at interfaces between the first and second internal electrodes and the dielectric layers, and a ratio of an area occupied by the secondary phase material to an overall area of the ceramic body is 0.1% to 0.5%. | 06-26-2014 |
Patent application number | Description | Published |
20090172913 | DUST SEPARATION APPARATUS OF VACCUM CLEANER - A distribution unit for a dust separating apparatus of a vacuum cleaner is provided. The distribution unit distributes air and dust to the dust separation unit includes a body having an inlet for introducing the air and dust to the body, a plurality of branch passages for distributing the air introduced into the body to the dust separation unit, and a main passage for connecting the inlet with the branch passages, and wherein a passage cross-sectional area of the main passage at the branch passage is greater than a passage cross-sectional area of the inlet. | 07-09-2009 |
20090293224 | VACUUM CLEANER AND DUST SEPARATING APPARATUS THEREOF - A dust separating apparatus for a vacuum cleaner is provided. The dust separating apparatus includes a cyclone configured to provide a plurality of cyclone airflows therein and a dust container provided separate from the cyclone. The cyclone includes a first air inlet configured to receive an airflow containing dust and a dust outlet configured to discharge dust separated by the plurality of cyclone airflows. The dust outlet is located in a central portion of the cyclone. The dust container is removably placeable into communication with the dust outlet to collect dust separated in the cyclone. A vacuum cleaner including the dust separating apparatus is also provided. | 12-03-2009 |
20100263161 | VACUUM CLEANER - A dust separating device for a vacuum cleaner is provided. The dust separating device includes a dust separating unit including a first main body movably connected to a second main body. The second main body includes a plurality of sub bodies coupled together. A vacuum cleaner is also provided. The vacuum cleaner includes a main vacuum cleaner body and a dust separating device including a dust separating unit and a filter unit. The dust separating device is detachably mounted to the main body and includes a plurality of main bodies. | 10-21-2010 |
20130258119 | COMMUNICATION SYSTEM AND METHOD OF TRANSMITTING AND RECEIVING DATA IN COMMUNICATION SYSTEM - A communication system and a method of transmitting and/or receiving data in the communication system are provided. A method of transmitting media data of a camera to a user terminal in a communication environment in which the camera connected to a first network and the user terminal connected to a third network are connected to a second network includes: obtaining second address information of the second network that corresponds to first address information of the first network, from an address conversion apparatus; obtaining third address information of the second network from an address providing apparatus connected to the second network; transmitting the first through third address information to the user terminal through a session control server connected to the second network; and transmitting the media data to the user terminal based on at least one of the first through third address information. | 10-03-2013 |
Patent application number | Description | Published |
20090065845 | Embedded semiconductor device and method of manufacturing an embedded semiconductor device - Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance. | 03-12-2009 |
20090246938 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of forming a semiconductor device includes forming a first chip region, a second chip region, and a scribe lane region between the first and second chip regions in a wafer, the wafer having a first surface and a second surface facing the first surface, and forming a penetrating extension hole and a scribe connector in the scribe lane region, the penetrating extension hole penetrating the wafer from the first surface to the second surface and extending along the scribe lane region, wherein the scribe connector connects the first and second chip regions spaced apart from each other by the penetrating extension hole. | 10-01-2009 |
20100059888 | Mask ROM and method of fabricating the same - A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes. | 03-11-2010 |
20100167487 | MASK ROM DEVICES AND METHODS FOR FORMING THE SAME - A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region. | 07-01-2010 |
20100320574 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of forming a semiconductor device includes forming a first chip region, a second chip region, and a scribe lane region between the first and second chip regions in a wafer, the wafer having a first surface and a second surface facing the first surface, and forming a penetrating extension hole and a scribe connector in the scribe lane region, the penetrating extension hole penetrating the wafer from the first surface to the second surface and extending along the scribe lane region, wherein the scribe connector connects the first and second chip regions spaced apart from each other by the penetrating extension hole. | 12-23-2010 |
20130208013 | APPARATUS AND METHOD FOR MANAGING OBJECT IN PORTABLE ELECTRONIC DEVICE - An apparatus and a method for displaying an object in a portable electronic device are provided. The method for displaying the object includes displaying at least one object according to a first arrangement, and when an object size change event occurs, changing a size of the at least one object and displaying the at least one object having the changed size by changing an object arrangement to a second arrangement. | 08-15-2013 |
20130227480 | APPARATUS AND METHOD FOR SELECTING OBJECT IN ELECTRONIC DEVICE HAVING TOUCHSCREEN - An apparatus and a method for selecting an object in an electronic device having a touchscreen are provided. The method for selecting an object, includes when a first touch is detected, setting a point of the first touch as a first reference point, and when movement of touch points from the first touch point is detected, selecting at least two objects, included in a first object selection area according to the first touch point and a first movement path of the touch points. | 08-29-2013 |
Patent application number | Description | Published |
20100157159 | Method and apparatus for processing video data of liquid crystal display device - A video processing method and apparatus for a liquid crystal display (LCD) device is disclosed. The video processing method for the LCD device includes detecting noise by comparing data of a previous frame with data of a current frame, if the noise is detected, removing the noise from the current frame data, and outputting the resultant current frame data having no noise together with the previous frame data, and comparing the previous frame data with the resultant current frame data having no noise in a lookup table, selecting overdriving data corresponding to the comparison result, and outputting the selected overdriving data. | 06-24-2010 |
20100164852 | LIQUID CRYSTAL DISPLAY DEVICE - Disclosed herein is a liquid crystal display device in which an image can be correctly seen even though a screen is rotated. The liquid crystal display device includes a storage unit for storing a plurality of screen change signals, and a timing controller for dividing image data of one horizontal line externally supplied thereto into k odd sub-image data and k even sub-image data, and sequentially outputting the k odd sub-image data and sequentially outputting the k even sub-image data. | 07-01-2010 |
20110141153 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DRIVING THE SAME - A liquid crystal display device includes: a liquid crystal panel that displays images using a plurality of pixels each including red, green and blue sub-pixels; a gate driving portion that supplies a gate signal to the liquid crystal panel; a data driving portion that supplies a data signal to the liquid crystal panel; and a timing control portion that compares difference of gray level between image signals corresponding to the red, green and blue sub-pixels with a first threshold value and compares difference of gray level between the image signals corresponding to the red, green and blue sub-pixels of neighboring pixels of the plurality of pixels in order to judge type of the image signals, and drives the data driving portion in different methods according to the type of the image signals. | 06-16-2011 |
20120146966 | Driving Circuit for Liquid Crystal Display Device and Method for Driving the Same - A driving circuit for a liquid crystal display device includes a liquid crystal panel comprising a plurality of pixel areas to display an image; a data driver configured to drive data lines of the liquid crystal panel; a gate driver configured to drive gate lines of the liquid crystal panel; and a timing controller configured to generate an internal enable signal in an initial driving where an external power is applied, to control the gate and data drivers, and configured to control the gate and data drivers based on synchronization signals, after controlling the driving of the gate driver to be stopped for one frame period when at least one synchronization signals are input from outside. | 06-14-2012 |
20120146967 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DRIVING THE SAME - The liquid crystal display device includes a display panel for displaying a picture thereon, first to (n)th upper data drive ICs for supplying pixel voltages to one side of each data line in the display panel, first to (n)th bottom data drive ICs for supplying pixel voltages to the other side of each data line, a first timing controller for generating an upper data control signal and for controlling operation of the upper data drive ICs, and a second timing controller for generating a bottom data control signal and for controlling operation of the bottom data drive ICs wherein at least one of the first and second timing controllers analyzes the picture data applied thereto and controls the polarities of the pixel voltages to be forwarded from the upper data drive ICs and the bottom data drive ICs with reference to the result of the analysis. | 06-14-2012 |
20140043305 | DISPLAY DEVICE AND METHOD OF DRIVING THE SAME - A display device including a display panel including gate and data line that cross each other; a first control signal generation unit generating a source output enable signal and a first gate output enable signal in synchronization with a data enable signal modulated according to a spread frequency clock signal; a second control signal generation unit counting a number of clocks of a fixed-frequency clock signal based on a point of time at which a logic high state of the source output enable signal ends, and outputting a second gate output enable signal when the number of the counted clocks becomes equal to a reference value; and a gate driving unit controlling outputting of a gate signal to the gate lines using the second gate output enable signal. | 02-13-2014 |
20140043317 | DISPLAY DEVICE AND METHOD OF DRIVING THE SAME - A display device including a display panel including gate and data line that cross each other; a first control signal generation unit generating a source output enable signal and a first gate output enable signal in synchronization with a data enable signal modulated according to a spread frequency clock signal; a second control signal generation unit starting to count a number of clocks of a fixed-frequency clock signal based on a point of time at which a first state of the source output enable signal ends, and outputting a second gate output enable signal when the counted number of the clocks becomes equal to a reference value; and a gate driving unit controlling an outputting of a gate signal to the gate lines using the second gate output enable signal. | 02-13-2014 |
Patent application number | Description | Published |
20160075023 | ROBOT MOTION REPLANNING BASED ON USER MOTION - The disclosure includes a system and method for determining a robot path based on user motion by determining a current position of a robot with a processor-based computing device programmed to perform the determining, receiving sensor readings on positions, directions, and velocities of a visually-impaired user and other users, generating a model of the motions of the visually-impaired user and the other users, the model including a user path for the visually-impaired user and a robot path for the robot, generating a collision prediction map to predict collisions between at least one of the robot, the visually-impaired user, and the other users, determining whether there is a risk of collision for either the visually-impaired user or the robot, and responsive to the risk of collision, updating at least one of the user path and the robot path. | 03-17-2016 |
20160132530 | IDENTIFICATION OF A DRIVER'S POINT OF INTEREST FOR A SITUATED DIALOG SYSTEM - A method for identifying a Point of Interest (POI) of a driver of a vehicle comprises: receiving voice data; receiving head movement data of the driver; determining a location of the vehicle and POIs around the location when the voice data is received; identifying potential POIs of the driver by analyzing the head movement data and a timing of the voice data using Gaussian Process Regression (GPR); and identifying the POI of the driver using a plurality of: a speed of the vehicle, density of surrounding POIs and visual salience. | 05-12-2016 |
Patent application number | Description | Published |
20120064463 | Method of Forming Micropatterns - Provided is a method of forming micropatterns, in which a line-and-space pattern is formed using a positive photoresist, and a spin-on-oxide (SOX) spacer is formed on two sidewalls of the line-and-space pattern and used in etching a lower layer, thereby doubling a pattern density. Accordingly, all operations may be performed in single equipment (lithography equipment) without taking a substrate out, and thus a high throughput is obtained, and concerns about pollution are very low. Moreover, as the line-and-space pattern is formed using a wet method by using a negative tone developer, line-width roughness (LWR) of the micropatterns may be improved compared to when a dry etching method is used. | 03-15-2012 |
20120064724 | Methods of Forming a Pattern of Semiconductor Devices - Methods of forming a pattern of a semiconductor device including performing a double patterning process without using an atomic layer deposition (ALD) oxide film are provided. The methods may include forming a mask pattern on a substrate; forming a chemical attach process (CAP) material layer covering at least a portion of the mask pattern; forming a CAP adhesive layer by adhering at least a portion of the CAP material layer to the mask pattern by using a first baking process and a first development process; forming an interlayer covering at least a portion of the mask pattern and the CAP adhesive layer; and removing the mask pattern and the interlayer while allowing the CAP adhesive layer to remain by using a second baking process and a second development process. | 03-15-2012 |
20130034965 | METHODS OF FORMING FINE PATTERNS USING DRY ETCH-BACK PROCESSES - In a method of fabricating patterns in an integrated circuit device, first mask patterns, sacrificial patterns, and second mask patterns are formed on a target layer such that the sacrificial patterns are provided between sidewalls of adjacent ones of the first and second mask patterns. The sacrificial patterns between the sidewalls of the adjacent ones of the first and second mask patterns are selectively removed using a dry etch-back process, and the target layer is patterned using the first and second mask patterns as a mask. | 02-07-2013 |