Park, Ichon
Chang Heon Park, Ichon KR
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20090117748 | METHOD FOR MANUFACTURING A PHASE CHANGE MEMORY DEVICE CAPABLE OF IMPROVING THERMAL EFFICIENCY OF PHASE CHANGE MATERIAL - A method for manufacturing a phase change memory device, capable of improving reset current characteristics of a phase change layer by preventing thermal loss of the phase change layer. An interlayer dielectric layer having a lower electrode contact is formed on a semiconductor substrate. A phase change layer and an upper electrode layer are sequentially formed on the interlayer dielectric layer. Then, an upper electrode and a phase change pattern are formed by etching predetermined portions of the upper electrode layer and the phase change layer using an etching gas having chlorine gas. | 05-07-2009 |
Heat Bit Park, Ichon KR
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20090207668 | DATA STROBE CLOCK BUFFER IN SEMICONDUCTOR MEMORY APPARATUS, METHOD OF CONTROLLING THE SAME, AND SEMICONDUCTOR APPARATUS HAVING THE SAME - A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal. | 08-20-2009 |
20110242910 | DATA STROBE CLOCK BUFFER IN SEMICONDUCTOR MEMORY APPARATUS, METHOD OF CONTROLLING THE SAME, AND SEMICONDUCTOR APPARATUS HAVING THE SAME - A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal. | 10-06-2011 |
Hyung Soon Park, Ichon KR
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20090127653 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized. | 05-21-2009 |
20110240950 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized. | 10-06-2011 |
Jae Boum Park, Ichon KR
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20080279031 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first buffer and a second buffer having different operational timing, a first voltage power supply for generating a first power supply voltage supplied to the first buffer in accordance with the operational timing of the first buffer, and a second voltage power supply for generating a second power supply voltage supplied to the second buffer in accordance with the operational timing of the second buffer. | 11-13-2008 |
20090002019 | APPARATUS FOR ADJUSTING RESISTANCE VALUE OF A DRIVER IN A SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for adjusting a resistance value of a driver of a semiconductor integrated circuit in which the resistance value of the driver is adjusted according to a code signal. The apparatus includes a control means that generates a plurality of counting mode signals such that the unit of counting is changed in a predetermined period, a counting means that counts the code signal in the unit of counting that is changed in response to the plurality of counting mode signals, according to a count up/down signal, and a comparing means that compares a voltage obtained by converting the code signal with a reference voltage to generate the count up/down signal. | 01-01-2009 |
Jum Yong Park, Ichon KR
Patent application number | Description | Published |
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20090127653 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized. | 05-21-2009 |
20110240950 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized. | 10-06-2011 |
Jung Hoon Park, Ichon KR
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20080253205 | WRITE CONTROL SIGNAL GENERATION CIRCUIT, SEMICONDUCTOR IC HAVING THE SAME AND METHOD OF DRIVING SEMICOUNDUCTOR IC - A write control signal generation circuit includes a delay/comparison/transmission block that outputs one of a delayed write command signal and a write command signal according to a test mode signal, and a control signal generation unit that generates a write control signal by delaying the output of the delay/comparison/transmission block corresponding to a variable amount of delay. | 10-16-2008 |
Ki Chon Park, Ichon KR
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20100067315 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD THEREOF - A semiconductor IC device includes a common column signal generating block providing precolumn strobe signals by using external command signals and a first group of bank addresses among a plurality of bank addresses, and a column strobe signal generating block providing a plurality of column strobe signals to selectively activate a plurality of banks by using the precolumn strobe signals and a second group of bank addresses among the plurality of bank addresses that are not used when the precolumn strobe signals are generated. | 03-18-2010 |
Kyoung-Wook Park, Ichon KR
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20090168570 | REDUNDANCY CIRCUIT USING COLUMN ADDRESSES - A redundancy circuit includes an address redundancy circuit block that compares column address information of a defective memory cell and an external input column address and outputs a redundancy column activation signal, and an input/output (IO) redundancy circuit block that, in response to IO fuse information, which is information about a sub-block where a column line of the defective memory cell is arranged, and the redundancy column activation signal, controls whether or not to activate a global IO line connected to an IO pad of the sub-block. | 07-02-2009 |
20090201735 | NON-VOLATILE MEMORY APPARATUS FOR CONTROLLING PAGE BUFFER AND CONTROLLING METHOD THEREOF - A non-volatile memory apparatus for controlling a page buffer includes a page buffer configured to include a plurality of buffer stages, each buffering input/output data of cell arrays in units of predetermined number of bits, and a control unit configured to selectively activate one of the plurality of buffer stages when a burst mode as a synchronous mode is activated. | 08-13-2009 |
Mun Phil Park, Ichon KR
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20080212394 | WRITE DRIVING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A write driving circuit includes a plurality of driving units that write data corresponding to detection signals on memory banks, and at least one detecting unit that detects data input from the outside, and outputs the detection signals to two or more driving units among the plurality of driving units. | 09-04-2008 |
20080253210 | SEMICONDUCTOR MEMORY APPARATUS - Disclosed is a semiconductor memory apparatus capable of improving precharge performance. The semiconductor memory apparatus includes a plurality of memory banks, data input/output lines commonly connected to the memory banks, and a plurality of precharge circuit units connected to the data input/output lines and aligned in an extension direction of the data input/output lines while being spaced apart from each other by a predetermined distance. | 10-16-2008 |
Nak Kyu Park, Ichon KR
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20080309368 | CIRCUIT FOR GENERATING ON-DIE TERMINATION CONTROL SIGNAL - A circuit for generating an on-die termination control signal can include a first signal generation block configured to generate a first signal to prevent a first on-die terminal control from being performed in a frequency/voltage switching period, a second signal generation block configured to generate a second signal to perform a second on-die termination control at an initial stage of operation, and a signal output block configured to generate the on-die termination control signal by combining the first and second signals. | 12-18-2008 |
20090121742 | APPARATUS AND METHOD OF CALIBRATING ON-DIE TERMINATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for calibrating on-die termination for a semiconductor integrated circuit includes a comparing unit that compares a code conversion voltage, which is obtained by converting an internal code into an analog voltage, with a reference voltage, and outputs a comparison result signal, a code control unit that compares a current comparison result signal and a previous comparison result signal, among comparison result signals obtained by sequential comparison operations by the comparing unit, to determine whether or not the levels thereof are the same, and outputs an external code update signal according to the comparison result, and a counter that increases or decreases the internal code according to the comparison result signal and outputs the internal code as an external code according to the external code update signal | 05-14-2009 |
20090206890 | RESET SIGNAL GENERATOR AND A METHOD FOR GENERATING RESET SIGNAL OF A SEMICONDUCTOR INTEGRATED CIRCUIT - A reset signal generator of a semiconductor integrated circuit includes a counter that counts a clock signal in response to activation of a power-up signal and activates a count-result signal when the counted value reaches a target value, and a reset signal generating unit that activates a reset signal in response to the activation of the count result signal. | 08-20-2009 |
20100019814 | SEMICONDUCTOR IC DEVICE AND DATA OUTPUT METHOD OF THE SAME - A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a core strobe signal, a core block configured to output data stored in a memory cell in response to the core strobe signal, a data output unit configured to latch data output from the core block according to a plurality of control signals and output the latched data in a predetermined order, and a controller configured to generate the plurality of control signals by using both the core strobe signal and the internal clock signal. | 01-28-2010 |
Sun Hwa Park, Ichon KR
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20100034036 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR CONTROLLING A SENSE AMPLIFIER - A semiconductor IC device includes a command decoder that provides internal read and internal write command signals in response to external command signals, and a delay control unit that is connected with the command decoder and provides an internal read command delay signal by controlling an activation timing of the internal read command signal in response to a test mode signal in a read mode. | 02-11-2010 |