Patent application number | Description | Published |
20080212387 | INTEGRATED CIRCUIT FUSE ARRAY - The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses. | 09-04-2008 |
20080212388 | INTEGRATED CIRCUIT FUSE ARRAY - The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses. | 09-04-2008 |
20080265962 | SCANNABLE FLIP-FLOP WITH NON-VOLATILE STORAGE ELEMENT AND METHOD - A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal. | 10-30-2008 |
20080266994 | LEVEL DETECT CIRCUIT - A detect circuit may be used to detect one or more characteristics corresponding to the fuse being programmed. When the one or more characteristics of the fuse being programmed reach the desired states or values, the programming of the fuse is discontinued. Thus, the programming duration for each fuse is customized for each fuse. As a result, for some embodiments, there may be fewer fuses that have been over-programmed. In addition, for some embodiments, the range of impedances of the programmed fuses have a narrower distribution of impedances due to the use of the detect circuit. | 10-30-2008 |
20100061162 | CIRCUIT AND METHOD FOR OPTIMIZING MEMORY SENSE AMPLIFIER TIMING - A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal. | 03-11-2010 |
20100198896 | RANDOM NUMBER GENERATOR - A random number generator includes a first one time programmable (OTP) element and a second OTP element. The first OTP element and second OTP element have a first distribution of probable values for an electrical characteristic when unprogrammed and a second distribution of probable values when programmed. A programming circuit applies a programming signal to the first OTP element and to the second OTP element that causes the first OTP element to switch from being unprogrammed to being programmed and having a first value for its electrical characteristic and the second OTP element to switch from being unprogrammed to being programmed and having a second value for its electrical characteristic. A sense amplifier provides an output signal at a first logic state when the first value exceeds the second value and at a second logic state when the second value exceeds the first value. | 08-05-2010 |
20110267869 | CIRCUIT FOR VERIFYING THE WRITE ENABLE OF A ONE TIME PROGRAMMABLE MEMORY - A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory. | 11-03-2011 |
20120194222 | MEMORY HAVING A LATCHING SENSE AMPLIFIER RESISTANT TO NEGATIVE BIAS TEMPERATURE INSTABILITY AND METHOD THEREFOR - An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal. A second NBTI compensation transistor includes a source electrode coupled to receive the reference voltage, a drain electrode coupled to a source electrode of the second inverter, and a gate electrode coupled to second logic responsive to the second data signal, wherein the second data signal is a logical complement of the first data signal. | 08-02-2012 |
20120327699 | WORD LINE FAULT DETECTION - In a memory having a word line driver and a ROM having N bit positions and a plurality of rows in which each row is coupled to a corresponding word line of the word line driver and stores a unique N bit value, a method includes activating, by the word line driver, a selected word line, and, for each bit position, determining whether a value of a true bit line of the bit position is at a same logic state as a value of a complementary bit line of the bit position when the word line driver activates the selected word line. In response to determining that a value of the true bit line is at the same logic state as the value of the complementary bit line for any of the N bit positions, providing a multiple word line fault indicator indicating that multiple word lines are activated simultaneously. | 12-27-2012 |
20140117953 | METHOD AND APPARATUS FOR A TUNABLE DRIVER CIRCUIT - A driver circuit having an adjustable output signal includes a logic circuit configured to receive an input signal into a first input terminal and an output circuit coupled to the logic circuit, wherein the output circuit is configured to generate, at an output terminal of the output circuit, an output signal having a signal level that changes in response to a signal level of the input signal. The driver circuit further includes a feedback circuit coupled to a second input terminal of the logic circuit. The feedback circuit includes first and second gate terminals coupled to the output terminal and a third gate terminal coupled to a control signal supply, wherein the feedback circuit is configured to control a maximum level of the output signal from the driver circuit based on an operating threshold of the feedback circuit as set by a control signal generated by the control signal supply. | 05-01-2014 |
20150085557 | MEMORY HAVING ONE TIME PROGRAMMABLE (OTP) ELEMENTS AND A METHOD OF PROGRAMMING THE MEMORY - A method of programming a memory includes selecting a logic state for programming a first bitcell of the memory. A first one-time-programmable (OTP) element of the first bitcell is programmed using a first set of conditions intended to achieve a first target resistance in accordance with the selected logic state which results in a first degree of programming of the first OTP element. A second OTP element of the first bitcell is programmed using a second set of conditions different from the first set of conditions intended to achieve a second target resistance in accordance with the selected logic state which results in a second degree of programming of the second OTP element, wherein the first and second degrees of programming are visually indistinguishable. | 03-26-2015 |
20150180452 | LOW LEAKAGE CMOS CELL WITH LOW VOLTAGE SWING - A CMOS cell incorporated on an integrated circuit including a PMOS transistor and an NMOS transistor. The current terminals of the PMOS and NMOS transistors are coupled in series between a lower voltage supply rail and a reference rail. The well connection of the PMOS transistor is coupled to an upper voltage supply rail having a voltage level greater than the lower voltage supply rail. The CMOS cell has low voltage swing and low leakage current to reduce power consumption. A second PMOS and NMOS transistor pair may be included and coupled in similar manner and to the first PMOS and NMOS pair to form a non-inverting cell. The PMOS transistors may be implemented in an N-well that is conductively tied to the upper supply voltage rail to avoid isolation barriers. The cell may be used in a clock tree to significantly reduce power consumption of the integrated circuit. | 06-25-2015 |
20150206594 | FUSE CIRCUIT WITH TEST MODE - During a program operation of a fuse cell of a fuse circuit, all of a group of select transistors of a fuse cell are made conductive to program the fuse cell. During a test operation of a fuse cell of the fuse circuit, less than all of the group of select transistors are made conductive so that current less than a programming current flows through the fuse cell. | 07-23-2015 |