Patent application number | Description | Published |
20080212282 | METHOD AND APPARATUS FOR COOLING AN EQUIPMENT ENCLOSURE THROUGH CLOSED-LOOP LIQUID-ASSISTED AIR COOLING IN COMBINATION WITH DIRECT LIQUID COOLING - A method and an apparatus for cooling, preferably within an enclosure, a diversity of heat-generating components, with at least some of the components having high-power densities and others having low-power densities. Heat generated by the essentially relatively few high-power-density components, such as microprocessor chips for example, is removed by direct liquid cooling, whereas heat generated by the more numerous low-power or low-watt-density components, such as memory chips for example, is removed by liquid-assisted air cooling in the form of a closed loop comprising a plurality of heating and cooling zones that alternate along the air path. | 09-04-2008 |
20080235942 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure. | 10-02-2008 |
20080245847 | Compliant Mold Fill Head with Integrated Cavity Venting and Solder Cooling - A mold fill head includes a solder delivery head and an interface portion having a compliant portion secured to the solder delivery head and a dispensing region associated with the compliant portion. The dispensing region is formed with at least one aperture configured to interface with cavities in a mold plate, the at least one aperture being in fluid communication with the solder delivery head. The compliant portion is configured and dimensioned to urge the dispensing region against the mold plate when held a predetermined distance therefrom and to substantially tolerate variations in flatness of the mold plate, variations in the predetermined distance, and/or variations in an angular orientation of the interface portion and the mold plate. | 10-09-2008 |
20080265406 | APPARATUS AND METHODS FOR COOLING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGES - Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers. | 10-30-2008 |
20080307645 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure. | 12-18-2008 |
20080311768 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure. | 12-18-2008 |
20080315403 | APPARATUS AND METHODS FOR COOLING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGES - Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers. | 12-25-2008 |
20090007427 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 01-08-2009 |
20090013528 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cros s-section and is constituted of a dielectric elastomeric material. At least one sidewall of the interposer is slitted to facilitate the venting of gases and pressure therethrough. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 01-15-2009 |
20090049688 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 02-26-2009 |
20090070999 | METHOD OF PRODUCING A LAND GRID ARRAY (LGA) INTERPOSER STRUCTURE PROVIDING FOR ELECTRICAL CONTACTS ON OPPOSITE SIDES OF A CARRIER PLANE - A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 03-19-2009 |
20090081891 | METHOD OF PRODUCING LAND GRID ARRAY (LGA) INTERPOSER GROUPS OF DIFFERENT HEIGHTS UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and interposer groupings of different height being mounted on a first surface of said carrier plane. Each interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of each hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 03-26-2009 |
20090100664 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. A plurality of slots are formed in the sidewall of said interposer for the venting of gases and pressure therethrough. | 04-23-2009 |
20090119916 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 05-14-2009 |
20090320282 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 12-31-2009 |
20100000085 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 01-07-2010 |
20100019377 | SEGMENTATION OF A DIE STACK FOR 3D PACKAGING THERMAL MANAGEMENT - An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM. | 01-28-2010 |
20100279521 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 11-04-2010 |
20110205708 | DOUBLE-FACE HEAT REMOVAL OF VERTICALLY INTEGRATED CHIP-STACKS UTILIZING COMBINED SYMMETRIC SILICON CARRIER FLUID CAVITY AND MICRO-CHANNEL COLD PLATE - A plurality of heat-dissipating electronic chips are arranged in a vertical chip stack. The electronic chips have electronic components thereon. A cold plate is secured to a back side of the chip stack. A silicon carrier sandwich, defining a fluid cavity, is secured to a front side of the chip stack. An inlet manifold is configured to supply cooling fluid to the cold plate and the fluid cavity of the silicon carrier sandwich. An outlet manifold is configured to receive the cooling fluid from the cold plate and the fluid cavity of the silicon carrier sandwich. The cold plate, the silicon carrier sandwich, the inlet manifold, and the outlet manifold are configured and dimensioned to electrically isolate the cooling fluid from the electronic components. A method of operating an electronic apparatus and a method of manufacturing an electronic apparatus are also disclosed. Single-sided heat removal with double-sided electrical input-output and double-sided heat removal with double-sided electrical input-output are also disclosed. | 08-25-2011 |
20120233510 | HIGH MEMORY DENSITY, HIGH INPUT/OUTPUT BANDWIDTH LOGIC-MEMORY STRUCTURE AND ARCHITECTURE - A chip stack structure includes a logic chip having an active device surface, and memory slices of a memory unit vertically aligned such that a surface of the memory slices is oriented perpendicular to the active device surface of the logic chip. The chip stack structure also includes wiring patterned on an upper surface of the memory slices, the wiring electrically connecting memory leads of the memory slices to logic grids corresponding to logic grid connections of the logic chip. | 09-13-2012 |
20130091867 | CONTAMINANT SEPARATOR FOR A VAPOR-COMPRESSION REFRIGERATION APPARATUS - Apparatuses and methods are provided for facilitating cooling of an electronic component. The apparatus includes a vapor-compression refrigeration system, which includes an expansion component, an evaporator, a compressor and a condenser coupled in fluid communication. The evaporator is coupled to and cools the electronic component. The apparatus further includes a contaminant separator coupled in fluid communication with the refrigerant flow path. The separator includes a refrigerant cold filter and a thermoelectric array. At least a portion of refrigerant passing through the refrigerant flow path passes through the cold filter, and the thermoelectric array provides cooling to the cold filter to cool refrigerant passing through the filter. By cooling refrigerant passing through the filter, contaminants solidify from the refrigerant, and are deposited in the cold filter. The separator may further include a refrigerant hot filter coupled to a hot side of the thermoelectric array for further filtering the refrigerant. | 04-18-2013 |
20130091871 | CONTAMINANT COLD TRAP FOR A VAPOR-COMPRESSION REFRIGERATION APPARATUS - Apparatuses and methods are provided for facilitating cooling of an electronic component. The apparatus includes a vapor-compression refrigeration system. The vapor-compression refrigeration system includes an expansion component, an evaporator and a compressor coupled in fluid communication via a refrigerant flow path. The evaporator is coupled to and cools the electronic component. The apparatus further includes a contaminant cold trap coupled in fluid communication with the refrigerant flow path. The cold trap includes a refrigerant cold filter and a coolant-cooled structure. At least a portion of refrigerant passing through the refrigerant flow path passes through the refrigerant cold filter, and the coolant-cooled structure provides cooling to the refrigerant cold filter to cool refrigerant passing through the filter. By cooling refrigerant passing through the filter, contaminants solidify from the refrigerant, and are deposited in the refrigerant cold filter. | 04-18-2013 |
20130091886 | INTRA-CONDENSER CONTAMINANT EXTRACTOR FOR A VAPOR-COMPRESSION REFRIGERATION APPARATUS - Apparatuses and methods are provided for facilitating cooling of an electronic component. The apparatus includes a vapor-compression refrigeration system. The vapor-compression refrigeration system includes an expansion component, an evaporator, a compressor, and a condenser coupled in fluid communication via a refrigerant flow path. The evaporator is coupled to and cools the electronic component. The apparatus further includes a contaminant extractor coupled in fluid communication with the refrigerant flow path. The extractor includes a refrigerant boiling filter and a heater. At least a portion of refrigerant passing through the refrigerant flow path passes through the refrigerant boiling filter, and the heater provides heat to the refrigerant boiling filter to boil refrigerant passing through the filter. By boiling refrigerant passing through the filter, contaminants are extracted from the refrigerant, and are deposited in the refrigerant boiling filter. | 04-18-2013 |
20130105994 | HEATSINK ATTACHMENT MODULE | 05-02-2013 |
20130151812 | NODE INTERCONNECT ARCHITECTURE TO IMPLEMENT HIGH-PERFORMANCE SUPERCOMPUTER - Node Interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link. | 06-13-2013 |
20130199752 | SEMICONDUCTOR DEVICE COOLING MODULE - A cooling module for cooling a semiconductor is provided and includes a land grid array (LGA) interposer, a substrate with an LGA side and a chip side, a cooler, a load frame attached to the substrate and formed to define an aperture in which the cooler is removably disposable, a spring clamp removably attachable to the load frame and configured to apply force from the load frame to the cooler such that the substrate and the cooler are urged together about the semiconductor and a load assembly device configured to urge the load frame and the LGA interposer together. | 08-08-2013 |
20130344660 | HEATSINK ATTACHMENT MODULE - An assembly process for a heatsink attachment module for a chip packaging apparatus is provided and includes attaching a semiconductor chip to a substrate to form a module subassembly, placing a load frame and shim in a fixture, dispensing adhesive to the load frame and loadably placing the module subassembly chip face down in the fixture. | 12-26-2013 |
20140021616 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure. | 01-23-2014 |
20140024146 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure. | 01-23-2014 |
20140053575 | CONTAMINANT SEPARATOR FOR A VAPOR-COMPRESSION REFRIGERATION APPARATUS - Apparatuses and methods are provided for facilitating cooling of an electronic component. The apparatus includes a vapor-compression refrigeration system, which includes an expansion component, an evaporator, a compressor and a condenser coupled in fluid communication. The evaporator is coupled to and cools the electronic component. The apparatus further includes a contaminant separator coupled in fluid communication with the refrigerant flow path. The separator includes a refrigerant cold filter and a thermoelectric array. At least a portion of refrigerant passing through the refrigerant flow path passes through the cold filter, and the thermoelectric array provides cooling to the cold filter to cool refrigerant passing through the filter. By cooling refrigerant passing through the filter, contaminants solidify from the refrigerant, and are deposited in the cold filter. The separator may further include a refrigerant hot filter coupled to a hot side of the thermoelectric array for further filtering the refrigerant. | 02-27-2014 |
20140071628 | CHIP STACK STRUCTURES THAT IMPLEMENT TWO-PHASE COOLING WITH RADIAL FLOW - A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold. | 03-13-2014 |
20140078672 | ELECTRONIC ASSEMBLY WITH DETACHABLE COOLANT MANIFOLD AND COOLANT-COOLED ELECTRONIC MODULE - Cooled electronic assemblies, and a method of decoupling a cooled electronic assembly, are provided. In one embodiment, the assembly includes a coolant-cooled electronic module with one or more electronic components and one or more coolant-carrying channels integrated within the module and configured to facilitate flow of coolant through the module for cooling the electronic component(s). In addition, the assembly includes a coolant manifold structure detachably coupled to the electronic module. The manifold structure, which includes a coolant inlet and outlet in fluid communication with the coolant-carrying channel(s) of the electronic module, facilitates flow of coolant through the coolant-carrying channel, and thus cooling of the electronic component(s). Coolant-absorbent material is positioned at the interface between the electronic module and the manifold structure to facilitate absorbing any excess coolant during a stepwise detaching of the manifold structure from the electronic module. | 03-20-2014 |
20140078704 | FUNCTIONAL GLASS HANDLER WAFER WITH THROUGH VIAS - A composite wiring circuit with electrical through connections and method of manufacturing the same. The composite wiring circuit includes a glass with first electrically-conducting through vias. The first electrically-conducting through vias pass from a top surface of the glass layer to a bottom surface of the glass layer. The composite wiring circuit further includes an interposer layer with second electrically-conducting through vias. The second electrically-conducting through vias pass from a top surface of the interposer layer to a bottom surface of the interposer layer. The second electrically-conducting through vias are electrically coupled to the first electrically-conducting through vias. | 03-20-2014 |
20140175635 | PACKAGING STRUCTURE - A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip. | 06-26-2014 |
20140179066 | PACKAGING STRUCTURE - A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip. | 06-26-2014 |
20140198452 | DISASSEMBLABLE ELECTRONIC ASSEMBLY WITH LEAK-INHIBITING COOLANT CAPILLARIES - Cooled electronic assemblies and methods of fabrication are provided. In one embodiment, the assembly includes a coolant-cooled electronic module with one or more electronic component(s), and one or more coolant-carrying channel(s) integrated within the module, and configured to facilitate flow of coolant through the module for cooling the electronic component(s). In addition, the assembly includes a coolant manifold structure detachably coupled to the electronic module. The manifold structure facilitates flow of coolant to the coolant-carrying channel(s) of the electronic module, and the coolant manifold structure and electronic module include adjoining surfaces. One surface of the adjoining surfaces includes a plurality of coolant capillaries or passages. The coolant capillaries are sized to inhibit, for instance, via surface tension, leaking of coolant therefrom at the one surface with decoupling of the coolant manifold structure and electronic module along the adjoining surfaces. | 07-17-2014 |
20140203428 | CHIP STACK WITH ELECTRICALLY INSULATING WALLS - A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint. | 07-24-2014 |
20140206143 | CHIP STACK WITH ELECTRICALLY INSULATING WALLS - A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads. | 07-24-2014 |
20140284040 | HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY - Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. | 09-25-2014 |
20140367749 | NANOCHANNEL PROCESS AND STRUCTURE FOR BIO-DETECTION - Nanochannel sensors and methods for constructing nanochannel sensors. An example method includes forming a sacrificial line on an insulating layer, forming a dielectric layer, etching a pair of electrode trenches, forming a pair of electrodes, and removing the sacrificial line to form a nanochannel. The dielectric layer may be formed on insulating layer and around the sacrificial line. The pair of electrode trenches may be etched in the dielectric layer on opposite sides of the sacrificial line. The pair of electrodes may be formed by filling the electrode trenches with electrode material. The sacrificial line may be removed by forming a nanochannel between the at least one pair of electrodes. | 12-18-2014 |
20140370637 | NANOCHANNEL PROCESS AND STRUCTURE FOR BIO-DETECTION - Nanochannel sensors and methods for constructing nanochannel sensors. An example method includes forming a sacrificial line on an insulating layer, forming a dielectric layer, etching a pair of electrode trenches, forming a pair of electrodes, and removing the sacrificial line to form a nanochannel. The dielectric layer may be formed on insulating layer and around the sacrificial line. The pair of electrode trenches may be etched in the dielectric layer on opposite sides of the sacrificial line. The pair of electrodes may be formed by filling the electrode trenches with electrode material. The sacrificial line may be removed by forming a nanochannel between the at least one pair of electrodes. | 12-18-2014 |
20150024549 | ALIGNMENT OF INTEGRATED CIRCUIT CHIP STACK - The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. | 01-22-2015 |
20150055949 | NODE INTERCONNECT ARCHITECTURE TO IMPLEMENT HIGH-PERFORMANCE SUPERCOMPUTER - Node interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link. | 02-26-2015 |