Fanucci
Luca Fanucci, Pistoia IT
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20090129390 | Method for transferring a stream of at least one data packet between first and second electric devices and corresponding device - Systems and methods for transferring a stream of at least one data packet between a first electronic device and second electronic device through a network-on-chip are disclosed. These systems and methods can comprise storing data packets in memory means provided in a network interface and transferring data packets from the memory means to the second electronic device. Packets can be transferred from the memory means after a quantity of packets is stored in the memory means, the quantity of packets being determined according to a value of a control parameter. | 05-21-2009 |
Luca Fanucci, Montecatini Terme (pistoia) IT
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20090063931 | Methods and architectures for layered decoding of LDPC codes with minimum latency - An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer. | 03-05-2009 |
Luca Fanucci, Montecatini Terme (pt) IT
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20130136129 | ZERO-CYCLE ROUTER FOR NETWORKS ON-CHIP - A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel. | 05-30-2013 |
20130156133 | Flexible Channel Decoder - A configurable Turbo-LDPC decoder comprising: | 06-20-2013 |
Luca Fanucci, Pisa IT
Patent application number | Description | Published |
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20150131333 | DC-DC CONVERTER WITH MULTIPLE OUTPUTS - A multiple output DC-DC converter comprises a transformer, a primary circuit, a plurality of secondary circuits, and a controller. The transformer has a primary and at least one secondary winding. The primary circuit connects to a DC power supply source and includes the primary winding of the transformer and a primary switch connected in series. The plurality of secondary circuits includes the at least one secondary winding of the transformer, wherein each secondary circuit provides a DC power supply output, and at least one of the secondary circuits has a secondary switch. The controller monitors an output signal of each secondary circuit and controls operation of the primary and secondary switches based on the monitored signals. The controller co-ordinates operation of the secondary switch with the primary switch, such that the primary switch and the secondary switch are switched on simultaneously, or with a controlled offset. | 05-14-2015 |