Patent application number | Description | Published |
20080212152 | SYSTEM AND METHOD FOR ENCRYPTION OF A HOLOGRAPHIC IMAGE - A system and method for encryption of a holographic image is disclosed. The method includes the operation of producing a beam of light having at least two wavelengths of light. The beam of light can be split to form an illumination beam and a reference beam. Amplitude information can be added to the illumination beam with an intensity control device to form an object beam. Wavelength information can be selected in the object beam to form a spatial color modulated object beam. The reference beam and spatial color modulated object beam can be directed to a predetermined location on the holographic media to interfere to record an interference pattern. | 09-04-2008 |
20080247012 | VARIABLE OPTICAL PHASE MODULATOR - A variable optical phase modulator includes an array of movable, micro-electromechanical conductive plates. Each conductive plate has a substantially reflective surface, and is responsive to an applied voltage to move the conductive plate normal to a plane of the array to a predetermined distance with respect to other conductive plates in the array. The phase modulator also includes a voltage controller associated with the array of conductive plates. The voltage controller supplies a voltage to at least one of the movable conductive plates to move and position the movable plate to change the phase of electromagnetic energy reflected from the reflective surface with respect to the phase of electromagnetic energy reflected from other conductive plates in the array. | 10-09-2008 |
20080247017 | SYSTEM AND METHOD FOR PRINTING A HOLOGRAM - A system and method for printing a hologram are disclosed. The method includes the operation of transmitting a laser light beam. The laser light beam can be split into an object beam and a reference beam. Phase information can be added to the object beam using a spatial phase modulator to form a phase controlled object beam. The reference beam and the phase controlled object beam can be directed to a predetermined location on a holographic media to enable the reference beam and the phase controlled object beam to form an interference pattern on the holographic media. | 10-09-2008 |
20080252690 | Micro Writing And Reading - In one embodiment, a printing device includes: a print engine configured to apply marking material to print media; a laser writer configured to expose the print media to a laser beam of sufficient energy to change the reflectivity of exposed portions of the print media; a media path along which the print engine may apply marking material to print media in a macro printing zone and along which the print media may be exposed to a beam of light emitted by the laser writer in a micro printing zone; and an electronic controller operatively connected to the print engine for selectively applying marking material to the print media and to the laser writer for selectively exposing the print media to a laser beam. | 10-16-2008 |
Patent application number | Description | Published |
20100199907 | BOUYANCY CONTROL DEVICE - A device having: a chamber having a gas inlet, a gas vent, and a liquid vent; and a float and a weight coupled to the chamber. The float has a lower density than the chamber. The weight has a higher density than the chamber. The aggregate density of the chamber, the float, and the weight is greater than the density of the chamber. The gas inlet, the gas vent, the liquid vent, the float, and the weight are positioned on the chamber such that: when the chamber is filled with and submerged in a liquid in which the chamber is neutrally-buoyant, the chamber is oriented to place the gas vent below the gas inlet; and when a gas is introduced through the gas inlet into the chamber that is filled with the liquid, the chamber pivots to raise the gas vent until a portion of the gas escapes from the chamber through only the gas vent. | 08-12-2010 |
20110229951 | BACTERIA-BASED GAS GENERATOR - Disclosed is an apparatus having: a pressure chamber and a gas-producing microorganism within the chamber. The pressure chamber is capable of maintaining a gas pressure of at least 0.5 psi above atmospheric pressure. | 09-22-2011 |
20110269207 | CELL AND BIOFACTOR PRINTABLE BIOPAPERS - Disclosed herein is a structure having: a porous polymeric film permeated by a first extracellular matrix material; and a topcoat layer comprising a second extracellular matrix gel disposed on the film. Also disclosed herein is a method of: providing a porous polymeric film; permeating the film with a first extracellular matrix material; and applying a topcoat layer of a second extracellular matrix material to the film. Also disclosed herein is a method of: laser-machining holes through a film comprising collagen to form a web-like structure. | 11-03-2011 |
20140154771 | CELL AND BIOFACTOR PRINTABLE BIOPAPERS - Disclosed herein is a structure having: a porous polymeric film permeated by a first extracellular matrix material; and a topcoat layer comprising a second extracellular matrix gel disposed on the film. Also disclosed herein is a method of: providing a porous polymeric film; permeating the film with a first extracellular matrix material; and applying a topcoat layer of a second extracellular matrix material to the film. Also disclosed herein is a method of: laser-machining holes through a film comprising collagen to form a web-like structure. | 06-05-2014 |
Patent application number | Description | Published |
20110131540 | Path Preserving Design Partitioning With Redundancy - Partitioning of a design allows STA to be performed in parallel on multiple, less demanding, and more available hardware resources. Therefore, runtime of STA can be significantly shortened. Notably, the partitioning can include redundancy. That is, partitions are allowed to share objects in order to preserve the timing path completeness and design structural integrity. Due to this redundancy, these partitions can account for many constraints specifically imposed by STA. Once these partitions are populated, analysis can be performed on those partitions in parallel to generate the same timing results as if the design had been analyzed flat as a single unit. Therefore, the performance of STA can be optimized without compromising the accuracy and quality of results. | 06-02-2011 |
20110307850 | RECURSIVE HIERARCHICAL STATIC TIMING ANALYSIS - A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block. | 12-15-2011 |
20120066656 | Parallel Parasitic Processing In Static Timing Analysis - A static timing analysis (STA) technique including a main process and a parallel process is described. In the main process, an IC design can be loaded and then linked to a cell library. Timing constraints to be applied to the IC design can be loaded. A timing update for the IC design can be performed. A report based on the timing update can be output. In the parallel process, the interconnect parasitics can be back-annotated onto the IC design. In one embodiment, the interconnect parasitics can be processed and stored on disk. Information on attaching to the stored parasitic data can be generated and provided to the main process during the step of performing the timing update. The parallel process can run concurrently and asynchronously with the main process. | 03-15-2012 |
20130227507 | Recursive Hierarchical Static Timing Analysis - A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block. | 08-29-2013 |