Patent application number | Description | Published |
20090026523 | PARTIALLY GATED FINFET - A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit. | 01-29-2009 |
20090032886 | SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS - A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction. | 02-05-2009 |
20090057780 | FINFET STRUCTURE INCLUDING MULTIPLE SEMICONDUCTOR FIN CHANNEL HEIGHTS - A semiconductor structure and a method for fabricating the semiconductor structure include a first semiconductor fin and a second semiconductor fin of the same overall height over a substrate. Due to the presence of a channel stop layer at the base of one of the first semiconductor fin and the second semiconductor fin, but not the other of the first semiconductor fin and the second semiconductor fin, the first semiconductor fin and the second semiconductor fin have different channel heights. The semiconductor fins may be used to fabricating a corresponding first finFET and a corresponding second finFET with differing performance characteristics due to the different channel heights of the first semiconductor fin and the second semiconductor fin. | 03-05-2009 |
20090059705 | SRAM HAVING ACTIVE WRITE ASSIST FOR IMPROVED OPERATIONAL MARGINS - A static random access memory (SRAM) is provided which includes a plurality of columns and a plurality of cells arranged therein. A voltage control circuit can be used to temporarily reduce a voltage at which power is supplied to cells belonging to a column selected for a write operation. The voltage control circuit may include a first p-type field effect transistor (PFET) and a second PFET. The first PFET may have a conduction path connected between a power supply and the cells belonging to the selected column. The second PFET may have a conduction path connected between the cells belonging to the selected column and ground. Such voltage control circuit may operate in a self-limited manner that avoids overshooting the reduced voltage level. In a variation thereof, a voltage control circuit having first and second NFETs (n-type field effect transistors) can be used to temporarily raise the voltage of a low voltage reference provided to cells of the SRAM. | 03-05-2009 |
20090059706 | SRAM ACTIVE WRITE ASSIST METHOD FOR IMPROVED OPERATIONAL MARGINS - A method is provided for controlling a voltage level supplied to a static random access memory (“SRAM”). In such method, when a column of the SRAM is selected for writing, a first p-type field effect transistor (“PFET”) and a second PFET can be operated to supply the power at a lower voltage level to cells belonging to a selected column, the lower voltage level being lower than the power supply voltage level. The first PFET can have a conduction path connected between a power supply and the cells belonging to the selected column. The second PFET may have a conduction path connected between the cells belonging to the selected column and ground. While supplying the power at the lower voltage level, a cell belonging to the selected column may be written. When the column is no longer selected for writing, the first and second PFETs can be operated to supply the power at the power supply voltage level again to the cells belonging to the selected column. | 03-05-2009 |
20090108287 | ONE-TRANSISTOR STATIC RANDOM ACCESS MEMORY WITH INTEGRATED VERTICAL PNPN DEVICE - A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed. | 04-30-2009 |
20090108351 | FINFET MEMORY DEVICE WITH DUAL SEPARATE GATES AND METHOD OF OPERATION - A FinFET device comprises a front gate (FG) and a separate back gate (BG) disposed on opposite sides of the fine. The fin structure may act as a floating body of a volatile memory cell. The front and back gates may be doped with the same or opposite polarity, and may be biased oppositely. A plurality of FinFETs may be connected in a memory array with single column erase, or double column erase capability. | 04-30-2009 |
20090108356 | INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES - A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer. | 04-30-2009 |
20090108374 | HIGH DENSITY SRAM CELL WITH HYBRID DEVICES - Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-up devices of the inverters and the pass gate devices are planar FETs or pull-down and pull-up devices of the inverters are FinFETs while the pass gate devices are planar FETs. | 04-30-2009 |
20090109733 | Design structure for sram active write assist for improved operational margins - A design structure embodied in a machine-readable medium used in a design process is provided. The design structure comprises a static random access memory (“SRAM”), including a plurality of cells arranged in an SRAM having a plurality of columns; and a voltage control circuit operable to temporarily raise a voltage level of a low voltage reference to cells belonging to a column selected for writing from the plurality of columns, wherein the voltage control circuit includes a first n-type field effect transistor (“NFET”) and a second NFET, the first NFET having a conduction path connected between ground and the low voltage reference, the second NFET having a conduction path connected between a power supply and the low voltage reference. | 04-30-2009 |
20090129191 | Structure for SRAM voltage control for improved operational margins - A design structure including a static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes voltage control circuits corresponding to respective ones of the plurality of columns of the array, each coupled to an output of a power supply. Each voltage control circuit temporarily reduces a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The power supply voltage to the selected column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column. | 05-21-2009 |
20090147560 | NOVEL SRAM CELL DESIGN TO IMPROVE STABILITY - A design structure embodied in a machine readable medium for use in a design process, the design structure representing a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, the SRAM cell is an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, the SRAM cell is a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions. | 06-11-2009 |
20090174010 | SRAM DEVICE STRUCTURE INCLUDING SAME BAND GAP TRANSISTORS HAVING GATE STACKS WITH HIGH-K DIELECTRICS AND SAME WORK FUNCTION - An SRAM semiconductor device includes: at least a first and a second field effect transistor formed on a same substrate, each of the transistors including a gate stack, each gate stack including a semiconductor layer disposed on a metal layer, the metal layer being disposed on a high-k dielectric layer located over a chemical region, wherein the metal layer of the first gate stack and the metal layer of the second gate stack have approximately a same work function, and wherein each channel region has approximately a same band gap. | 07-09-2009 |
20090186476 | STRUCTURE AND METHOD FOR IMPROVED SRAM INTERCONNECT - A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a cap layer; etching the exposed portion of the cap layer for revealing a portion of the silicon layer; etching the potion of the silicon layer, in which a portion of said silicon layer connects at least a portion of pull-down device of said SRAM to at least a portion of pull-up device of said SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. An interconnect structure is also provided. | 07-23-2009 |
20100295132 | PROGRAMMABLE PN ANTI-FUSE - Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p− substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p− substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse. | 11-25-2010 |
20110079921 | GENERATION OF METAL HOLES BY VIA MUTATION - A semiconductor interconnect architecture provides a reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) without degradation of the product yield or robustness, or increases copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs. | 04-07-2011 |
20110280094 | Boost Cell Supply Write Assist - A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source powering the SRAM circuit. | 11-17-2011 |
20120126339 | SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS - A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction. | 05-24-2012 |
20130037864 | CROSS-COUPLING OF GATE CONDUCTOR LINE AND ACTIVE REGION IN SEMICONDUCTOR DEVICES - Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme. | 02-14-2013 |
20130119481 | FINFET DEVICE - A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate. | 05-16-2013 |
20140113417 | CROSS-COUPLING OF GATE CONDUCTOR LINE AND ACTIVE REGION IN SEMICONDUCTOR DEVICES - Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme. | 04-24-2014 |
20140175564 | FINFET DEVICE - A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate. | 06-26-2014 |