Patent application number | Description | Published |
20090059641 | MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory die coupled to a plurality of through wafer interconnects (TWI), and a second memory die having a plurality of memory arrays disposed on the first memory die, the second memory die including a plurality of vias, wherein the plurality of vias are configured to allow the plurality of TWI to pass through the second memory die. The second memory die may be coupled to a second plurality of TWI. In this way, the interface chip may be used to communicatively couple the first memory die and the second memory die using the first and second plurality of TWI. Other apparatus, systems, and methods are disclosed. | 03-05-2009 |
20090210600 | MEMORY DEVICE WITH NETWORK ON CHIP METHODS, APPARATUS, AND SYSTEMS - Apparatus, method and systems are provided such as those that can include a processor module, an interface device disposed above or below the processor module, the interface device including a plurality of routing elements, at least one memory device disposed above or below the interface device and including a plurality of memory arrays, the plurality of memory arrays coupled to the interface device using a plurality of interconnects provided in vias provided in at least one of the memory device and the interface device. In addition, the interface device communicatively can couple the plurality of memory arrays to the processor module using the plurality of routing elements and the interconnects. | 08-20-2009 |
20100005238 | MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE - Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults. | 01-07-2010 |
20100061134 | MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems may include a substrate and a first memory device coupled to the substrate using a through wafer interconnect (TWI). An example may include an interface chip having a via to accommodate connection of the memory device to the substrate. Other apparatus, systems, and methods are disclosed. | 03-11-2010 |
20100085825 | STACKED DEVICE REMAPPING AND REPAIR - Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. | 04-08-2010 |
20100088460 | MEMORY APPARATUS, SYSTEMS, AND METHODS - Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed. | 04-08-2010 |
20100095168 | EMBEDDED PROCESSOR - Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed. | 04-15-2010 |
20100110745 | SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE - Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated. | 05-06-2010 |
20100165692 | VARIABLE MEMORY REFRESH DEVICES AND METHODS - Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate. | 07-01-2010 |
20100180150 | SYSTEMS AND METHODS FOR MONITORING A MEMORY SYSTEM - Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device. | 07-15-2010 |
20100191999 | MEMORY DEVICE POWER MANAGERS AND METHODS - Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power management of portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 07-29-2010 |
20100192041 | MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS - Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed. | 07-29-2010 |
20100195421 | STACKED-DIE MEMORY SYSTEMS AND METHODS FOR TRAINING STACKED-DIE MEMORY SYSTEMS - Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to at least one receive register, and/or a set of memory array timing signals to access a memory array on a die associated with a stacked-die memory vault. Systems and methods herein also include those that perform data eye training operations and/or memory array timing training operations associated with the stacked-die memory vault. | 08-05-2010 |
20100238693 | CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS - Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 09-23-2010 |
20110004722 | DATA TRANSFER MANAGEMENT - Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described. | 01-06-2011 |
20110060888 | STACKED DEVICE REMAPPING AND REPAIR - Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described. | 03-10-2011 |
20110167319 | ERROR CORRECTION IN A STACKED MEMORY - Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed. | 07-07-2011 |
20110185240 | EMBEDDED PROCESSOR - Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed. | 07-28-2011 |
20110194369 | VARIABLE MEMORY REFRESH DEVICES AND METHODS - Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate. | 08-11-2011 |
20110264858 | MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE - Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults. | 10-27-2011 |
20110267865 | CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS - Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 11-03-2011 |
20120023376 | SYSTEMS AND METHODS FOR MONITORING A MEMORY SYSTEM - Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device. | 01-26-2012 |
20120159270 | MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS - Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed. | 06-21-2012 |
20120218803 | MEMEORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems may include an interface chip, a first memory die having at least one memory array disposed on the interface chip, and a second memory die having at least one memory array disposed on the first memory die. The first memory die can include a plurality of vias configure allow a first plurality of through wafer interconnects (TWIs) to couple the interface chip with the second memory die, and the interface chip can be configured to communicatively couple the first memory die and the second memory die. Other apparatus, systems, and methods are disclosed. | 08-30-2012 |
20120221911 | EMBEDDED PROCESSOR - Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed. | 08-30-2012 |
20120250388 | VARIABLE MEMORY REFRESH DEVICES AND METHODS - Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate. | 10-04-2012 |
20120257434 | CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS - Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 10-11-2012 |
20120297241 | SYSTEMS AND METHODS FOR MONITORING A MEMORY SYSTEM - Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device. | 11-22-2012 |
20120320688 | SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE - Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated. | 12-20-2012 |
20130003473 | STACKED DEVICE REMAPPING AND REPAIR - Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described. | 01-03-2013 |
20130031303 | STACKED MEMORY DEVICES, SYSTEMS, AND METHODS - Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed. | 01-31-2013 |
20130042030 | DATA TRANSFER MANAGEMENT - Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described. | 02-14-2013 |
20130083585 | MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems for memory system are provided. In an example, a memory system can include a plurality of memory dice and an interface chip. The memory dice can include a first memory die including a memory array coupled to through wafer interconnects (TWIs) and a second memory die, wherein the first memory die is stacked over the second memory die. In an example, the interface chip can be coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice. In an example, the interface chip can be configured to perform DRAM sequencing. | 04-04-2013 |
20130097471 | ERROR CORRECTION IN A STACKED MEMORY - Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed. | 04-18-2013 |
20130145098 | MEMORY PREFETCH SYSTEMS AND METHODS - Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a stacked-die memory system when a pipeline associated with the selected memory vault is empty. | 06-06-2013 |
20130179740 | MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS - Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed. | 07-11-2013 |
20130329510 | STACKED DEVICE REMAPPING AND REPAIR - Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described. | 12-12-2013 |
20130346820 | EMBEDDED PROCESSOR - Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed. | 12-26-2013 |
20140063942 | MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems for memory system are provided. In an example, an interface chip can include a memory controller configured to couple to a processor and to couple to a plurality of stacked memory arrays using a data bus and a maintenance bus, wherein the data bus is separate from the maintenance bus, the plurality of stacked memory arrays forming two or more memory chips, the memory controller configured to control access to memory locations within the plurality of stacked memory arrays. | 03-06-2014 |
20140068190 | STACKED MEMORY DEVICES, SYSTEMS, AND METHODS - Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed. | 03-06-2014 |
20140112046 | CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS - Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. | 04-24-2014 |
20140112085 | SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE - Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated. | 04-24-2014 |
20140156946 | MEMORY PREFETCH SYSTEMS AND METHODS - Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a stacked-die memory system when a pipeline associated with the selected memory vault is empty. | 06-05-2014 |
20140204690 | STACKED-DIE MEMORY SYSTEMS AND METHODS FOR TRAINING STACKED-DIE MEMORY SYSTEMS - Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to at least one receive register, and/or a set of memory array timing signals to access a memory array on a die associated with a stacked-die memory vault. Systems and methods herein also include those that perform data eye training operations and/or memory array timing training operations associated with the stacked-die memory vault. | 07-24-2014 |
20140223069 | DATA TRANSFER MANAGEMENT - Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described. | 08-07-2014 |
20140281204 | FLEXIBLE MEMORY SYSTEM WITH A CONTROLLER AND A STACK OF MEMORY - Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults. | 09-18-2014 |
20140281693 | APPARATUSES AND METHODS FOR MEMORY TESTING AND REPAIR - Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information. | 09-18-2014 |
20140351503 | MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE - Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults. | 11-27-2014 |