Lo, Hsinchu City
Bin-Hau Lo, Hsinchu City TW
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20120092934 | MULTIPLEXING CIRCUIT - A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line. | 04-19-2012 |
20130229879 | METHOD OF USING MULTIPLEXING CIRCUIT FOR HIGH SPEED, LOW LEAKAGE, COLUMN-MULTIPLEXING MEMORY DEVICES - In at least one embodiment, a multiplexer has a plurality of sub-circuits, and each of the plurality of sub-circuits has a first transistor, a second transistor, and a third transistor. Drains of the first transistors are coupled with a first terminal of a fourth transistor, and drains of the second transistors are coupled with a second terminal of the fourth transistor. In at least one embodiment, a method of outputting data using the multiplexer includes turning on the second transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information. The second transistor of a non-selected one of the plurality of sub-circuits is turned off. The fourth transistor is turned on responsive to the clock signal. | 09-05-2013 |
20130258747 | METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT - A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold. | 10-03-2013 |
20150131394 | METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT - A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold. | 05-14-2015 |
Cheng-Yao Lo, Hsinchu City TW
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20130213817 | METHOD FOR SHRINKING LINEWIDTH OF EXTREME DIMENSION - A method for shrinking a linewidth on a substrate includes the steps of applying a stretching force on the substrate, defining a line on a top surface of the substrate and releasing the applied stretching force. The applied force is executed by mechanical stretching or thermal expansion and has a direction parallel to the line. | 08-22-2013 |
Chen-Lung Lo, Hsinchu City TW
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20100060841 | Flexible Display Panel - A flexible display panel comprises a flexible substrate, a display module, a driving unit and at least one anisotropic conductive film. The display module is disposed on the flexible substrate, and has a display area and a peripheral circuit area beside the display area. The anisotropic conductive film is connected between the peripheral circuit area and the driving unit, and the driving unit is electrically connected to the peripheral circuit area through the anisotropic conductive film. In addition, the anisotropic conductive film has an insulation film and a plurality of conductive particles disposed in the insulation film. Diameters of the conductive particles are in a range from 4.5 micrometers to 7 micrometers, and a distribution density of the conductive particles is a range from 45000 grains per square millimeter to 65000 grains per square millimeter. Therefore, the flexible display panel has high reliability. | 03-11-2010 |
Chi Lo, Hsinchu City TW
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20120281471 | Memory Page Buffer - Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement. | 11-08-2012 |
20130235674 | MEMORY PAGE BUFFER - Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement. | 09-12-2013 |
20140254297 | METHOD AND APPARATUS FOR MEMORY REPAIR - An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns. | 09-11-2014 |
20140258811 | STORAGE SCHEME FOR BUILT-IN ECC OPERATIONS - A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations. | 09-11-2014 |
Chiao-Jung Lo, Hsinchu City TW
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20120086653 | NAVIGATIONAL OPERATION METHOD - A navigational operation method, applied to a remote controller of a multi-media player, includes the following steps. One of multiple operation modes of the multi-media player is selected. A navigation key on the remote controller is triggered. A function table or multiple function keys corresponding to the selected operation mode are displayed on the multi-media player. | 04-12-2012 |
20120086858 | DISPLAY AND MULTI-VIEW DISPLAYING SWITCH METHOD THEREOF - A multi-view displaying switch method of a display includes the following steps. The display receives multiple channel signals, and captures multiple corresponding static images from the channel signals. The display displays the static images in a first multi-view pattern, and displays one multi-view switch key on the display. When the multi-view switch key is triggered, the display switches the first multi-view pattern to a second multi-view pattern to display the static images. | 04-12-2012 |
Chich-Lun Lo, Hsinchu City TW
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20150243939 | CAP ASSEMBLY FOR BATTERY - A cap assembly for a battery includes a roll combination member, a terminal combination member, an electrode terminal, a strength reinforcing block, a cap, and a pad assembly. The roll combination member includes at least one opening, so that terminal disposed portions of 2k rolls are capable of passing through the opening and k is an integer greater than 1, wherein one terminal disposed portion is formed by bending portions of central members of two adjacent rolls. The terminal combination member, the electrode terminal, the strength reinforcing block, the cap, and the pad assembly are sequentially combined on the roll combination member, wherein the electrode terminal includes an electrically conductive portion and a thermally conductive portion which surrounds the electrically conductive portion. The cap assembly is electrically connected to the bending portions at the same side of the 2k rolls. | 08-27-2015 |
Chieh-Chun Lo, Hsinchu City TW
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20120169898 | IMAGE CAPTURING APPARATUS AND BOOTING METHOD THEREOF - An image capturing apparatus and a booting method thereof are provided. In the method, a power-on signal is received, and then memory card plug information is read to determine whether a memory card of the image capturing apparatus has been plugged out in a power-off period of the image capturing apparatus. If it is determined that the memory card has not been plugged out, a previously recorded free space and a previously recorded file index table of the memory card are directly read, so as to accordingly boot the image capturing apparatus. If it is determined that the memory card has been plugged out, the free space of the memory card is re-calculated and a file sorting procedure is executed to generate the file index table, so as to accordingly boot the image capturing apparatus. | 07-05-2012 |
20130013846 | METHOD FOR STORING DATA AND ELECTRONIC APPARATUS USING THE SAME - A method for storing data and an electronic apparatus using the same are provided. Only data is written to a memory card when the electronic apparatus wants to store the data to the memory card. And file information and location information corresponding to the data stored in the memory card are recorded into a buffer block of the electronic apparatus. After a file closing action is executed, the file information and the location information recorded in the buffer block are written to the memory card. | 01-10-2013 |
Chih-Hsuan Lo, Hsinchu City TW
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20140333369 | KEY MODULE AND SIGNAL GENERATING METHOD THEREOF - A key module and a signal generating method of the key module are provided. The key module is suitable for an electronic device, the electronic device has a processing system, and the key module includes a detecting module and a controller. The detecting module includes a main electrode conductor and an assisting electrode conductor, where the assisting electrode conductor is disposed around the main electrode conductor. The controller is coupled to the main electrode conductor and the assisting electrode conductor. When the controller determines that a touch is detected by the main electrode conductor, but not detected by the assisting electrode conductor, the controller transmits a key signal to the processing system. | 11-13-2014 |
Chih-Yen Lo, Hsinchu City TW
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20140325311 | HYBRID ERROR CORRECTION METHOD AND MEMORY REPAIR APPARATUS THEREOF - A hybrid error correction method and a memory repair apparatus thereof are provided for a dynamic random access memory (DRAM). The memory repair apparatus includes a mode register and a hybrid error correction code and redundancy (HEAR) module. When the DRAM enters a standby mode, the mode register switches the DRAM to be controlled by the HEAR module. The HEAR module generates parity data of the error correction code within a default refresh period. The HEAR module extends the refresh period of the DRAM and uses the parity data for error detection to locate a data retention error in the DRAM until the maximum allowable refresh period supported by the HEAR module is reached. Before the DRAM returns to a working mode from a standby mode, the HEAR module performs an error correction process according to fail bit data and writes corrected data into the DRAM. | 10-30-2014 |
Chi-Kang Lo, Hsinchu City TW
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20120014087 | SIMPLE DETACHABLE ILLUMINATION STRUCTURE AND LAMP TUBE - A simple detachable illumination lamp tube includes a tube unit, a heat-dissipating unit, a light-emitting unit, a support unit and a lateral cover unit. The tube unit has a light-permitting hollow tube. The heat-dissipating unit has a heat-dissipating substrate received in the light-permitting hollow tube. The heat-dissipating substrate has two opposite lateral sides contacting the inner surface of the light-permitting hollow tube. The light-emitting unit has a plurality of strip light-emitting modules received in the light-permitting hollow tube. The strip light-emitting modules are disposed on the heat-dissipating substrate and electrically connected in sequence. The support unit has a plurality of support elements received in the light-permitting hollow tube and disposed between a bottom side of the heat-dissipating substrate and the inner surface of the light-permitting hollow tube. The lateral cover unit has two lateral covers installed on two ends of the light-permitting hollow tube. | 01-19-2012 |
20120069583 | LAMP HEAD ASSEMBLY AND LIGHTING LAMP TUBE - A lamp head assembly includes an outer head unit, an inner head unit, and an elastic pressing unit. The outer head unit includes at least two conductive pins. The inner head unit is disposed rotatably in the outer head unit. The elastic pressing unit is disposed movably in the outer head unit for selectively positioning the position of the inner head unit relative to the outer head unit or the position of the outer head unit relative to the inner head unit, wherein the elastic pressing unit includes a pressing element selectively exposed from the outer head unit. | 03-22-2012 |
Ching-Shyang Lo, Hsinchu City TW
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20130286210 | Bird-View Image Capture System and Bird-View Image Capture Method Thereof - A bird-view image capture system and a bird-view image capture method thereof. The system comprises a plurality of image capture modules, a processing module, a compositing module and a display module. Therein, each of the plurality of image capture modules captures an image respectively. The processing module analyzes the plurality of images to get a plurality of first images and a plurality of second images. The processing module converts the plurality of first images and the plurality of second images respectively to get a plurality of inboard images and a plurality of outboard images. The compositing module composes the plurality of inboard images and the plurality of outboard images as a plurality of compositing images. The compositing module composes each compositing image to produce a bird-view image. The display module displays the bird-view image. | 10-31-2013 |
Ching-Yu Lo, Hsinchu City TW
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20100123224 | HIGH MECHANICAL STRENGTH ADDITIVES FOR POROUS ULTRA LOW-K MATERIAL - A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group. | 05-20-2010 |
20110115088 | INTERCONNECT WITH FLEXIBLE DIELECTRIC LAYER - An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion. | 05-19-2011 |
20120074535 | LOW DIELECTRIC CONSTANT MATERIAL - The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH | 03-29-2012 |
Chiu-Mei Lo, Hsinchu City TW
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20160095683 | DECIDUOUS TEETH STORAGE DEVICE - The deciduous teeth storage device contains an openable casing, an upper gum cast, a lower gum cast, and a number of artificial teeth. The gum casts are stored in the casing. Along a gum model of the upper and lower gum casts, there are a number of holes for receiving the artificial teeth and the deciduous teeth, and the upper and lower gum casts are joined along their back edges by a foldable element providing an angle of rotation in-between. The casing contains a lower chamber where a movable drawer is configured for storing adhesives and artificial teeth. A transparent plate is attached to an upper side of the casing, and at least a pair of magnets are correspondingly embedded in the transparent plate and the top side of the casing, respectively, so that a child's photo can be positioned between the casing and the transparent plate. | 04-07-2016 |
Chi-Wei Lo, Hsinchu City TW
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20160065180 | SAMPLING CIRCUIT AND MASTER-SLAVE FLIP-FLOP - A sampling circuit includes a first latch, a second latch and a signal transition detector. The first latch is disposed on an upstream side of a logic circuit. The second latch is disposed on a downstream side of the logic circuit. The first latch and the second latch respectively switch to opposite states of an opaque state or a transparent state according to trigger signals generated by a reference clock and a control clock. The signal transition detector is configured for detecting whether the signal outputted by the logic circuit is in error or not and outputting a corresponding control clock. The above-mentioned sampling circuit can delay switching the second latch to the opaque state and switching the first latch to the transparent state to correct sampling when a timing error occurs. | 03-03-2016 |
Chung-Ming Lo, Hsinchu City TW
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20150098686 | CLOUD-BASED VIDEO MONITORING - One embodiment of the present invention provides a cloud-based video monitoring system comprising a camera and a network video recorder (NVR). During operation, the camera stores in a buffer last predetermined temporal segment of a video. The camera also stores a first video file in a local storage corresponding to an event detected by the camera. This first video file is non-overlapping with a second video file corresponding to the event and this second video file is stored in the NVR. The camera generates a third video file by pre-pending last predetermined temporal segment of a video prior to the event to the first video file and sends the third video file to the NVR. | 04-09-2015 |
Chun-Yuan Lo, Hsinchu City TW
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20130044548 | FLASH MEMORY AND MEMORY CELL PROGRAMMING METHOD THEREOF - A flash memory and a memory cell programming method thereof are provided. The programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of the memory cell. A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell. | 02-21-2013 |
Fu-Shun Lo, Hsinchu City TW
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20150228516 | APPARATUS AND OPERATION METHOD THEREOF - An apparatus includes a body and a surface for receiving a semiconductor wafer carrier is provided. A nozzle and a venting hole are provided on the surface. The semiconductor wafer carrier has at least one selectively closable capped opening at a bottom, top and/or side surface thereof. The capped opening is configured to couple to, and be accessible by, the nozzle and receive gas output from the nozzle so as to create a substantially oxygen free environment within the semiconductor wafer carrier. The vent hole is configured to allow gas to flow out of the semiconductor wafer carrier. In addition, the apparatus includes a sensor and a controller. The sensor is configured to monitor an ambient condition in the semiconductor wafer carrier, and the controller is configured to adjust a control valve based on the ambient condition so as to control the gas flow or output from the nozzle. | 08-13-2015 |
Han-Tang Lo, Hsinchu City TW
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20150116701 | DEFECT INSPECTION APPARATUS AND METHOD - A defect inspection apparatus is disclosed that includes a stage, a photosensitive element, and a controller. The stage can support a semiconductor element that has a plurality of complete dies and partial dies surrounding the complete dies. The photosensitive element is located above the stage. The controller is electrically connected to the photosensitive element to drive the photosensitive element to inspect the defects of the complete dies and the partial dies. | 04-30-2015 |
Hsiaoyun Lo, Hsinchu City TW
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20150035159 | SEMICONDUCTOR DEVICE HAVING BACKSIDE INTERCONNECT STRUCTURE ON THROUGH SUBSTRATE VIA AND METHOD OF FORMING THE SAME - A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer. | 02-05-2015 |
Jen-Wei Lo, Hsinchu City TW
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20100181377 | CARD READER WITH NEAR FIELD COMMUNICATION FUNCTION AND NEAR FIELD COMMUNICATION DEVICE THEREOF - A card reader with a near field communication (NFC) function is provided. The card reader includes a connector for connecting a host, a radio frequency (RF) antenna, and a circuit board having a secure digital (SD) reader chip and a micro SD interface slot. The micro SD interface slot has two RF pads coupled to the RF antenna, and a micro SD memory card having a flash memory chip, a control circuit, and a smart card circuit is inserted into the micro SD interface slot in a detachable manner. Thereby, the host can access data in the flash memory chip through the SD reader chip and the micro SD interface slot, and the smart card circuit can perform a NFC through the RF antenna and the micro SD interface slot. | 07-22-2010 |
Kuo-Chang Lo, Hsinchu City TW
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20150145743 | ANTENNA STRUCTURE - An antenna structure is disclosed. The antenna structure includes a symmetrizing portion and two radiation portions. The symmetrizing portion has an axis and two radiation portions are symmetrically connected to the symmetrizing portion along the axis. Each of the two radiation portions is formed in a boot shape within a quadrilateral region having a first edge with a first length, a second edge with a second length, a third edge with a third length and a fourth edge with a fourth length. Each radiation portion includes a first side having a length being equivalent to the first length, a second side having a length being equivalent to the second length, a third side having a length being at least one-sixth of the third length, a fourth side having a length being at least one-fifth of the fourth length, and a fifth side connecting the third side and the fourth side and forming an arc, wherein the arc follows a quarter trajectory of an ellipse. | 05-28-2015 |
Kuo-Shu Lo, Hsinchu City TW
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20090256682 | PRODUCT MANAGING SYSTEM AND METHOD USING RFID TECHNOLOGY - A product managing system and method using RFID technology is provided. The product managing system includes an RFID tag, an RFID reader, and a server. The RFID tag is set on a product for providing a tag ID, an object type and attribute, and an event content. The RFID reader reads the RFID tag. The server obtains various information provided by the RFID tag set on the product from the RFID reader, determines the product ID according to the tag ID, determines a class of the product and whether the product is correctly combined with another product according to the object type and attribute, and determines whether a processing procedure of the product is correctly conducted according to the event content. The server finally determines whether the product is normal according to the aforementioned determinations. | 10-15-2009 |
Li-Di Lo, Hsinchu City TW
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20120013367 | Power stage control circuit - The present invention discloses a power stage control circuit including: a driver circuit for controlling a power stage according to an error amplified signal; an error amplifier circuit for comparing a feedback voltage at a feedback terminal with a reference signal to generate the error amplified signal; a current generator circuit coupled to the feedback terminal for generating a fault detection current flowing to the feedback terminal; and a feedback terminal short detection circuit for generating a fault signal to stop the operation of the power stage when the feedback voltage is smaller than a short-circuit threshold voltage or when the fault detection current is larger than a short-circuit threshold current. | 01-19-2012 |
Li Sheng Lo, Hsinchu City TW
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20110079717 | INFRARED POSITIONING APPARATUS AND SYSTEM THEREOF - An infrared positioning apparatus comprises a plurality of infrared diodes, a plurality of amplifying units, a plurality of converting units and a positioning unit. The plurality of infrared diodes is configured to detect at least one infrared signal. The plurality of amplifying units are configured to amplify the at least one infrared signal for obtaining at least one amplified signal. The plurality of converting units are configured to convert the at least one amplified signal for obtaining at least one strength value of the at least one amplified signal. The positioning unit is configured to obtain the emitting direction of the at least one infrared signal in accordance with the at least one strength value of the at least one amplified signal. | 04-07-2011 |
Man-Yin Lo, Hsinchu City TW
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20090035575 | METHOD FOR MANUFACTURING METAL NANO PARTICLES HAVING HOLLOW STRUCTURE AND METAL NANO PARTICLES MANUFACTURED BY THE METHOD - A method for manufacturing metal nano particles having a hollow structure is provided. First, a suitable reducing agent is added into a first metal salt solution, and first metal ions are reduced to form first metal nano particles. Next, after the reducing agent is decomposed, a second metal salt solution with a higher reduction potential than that of the first metal is added. Then, the first metal particles are oxidized to form first metal ions when the second metal ions are reduced on the surface of the first metal by electrochemical oxidation reduction reaction, and thus, second metal nano particles having a hollow structure and a larger surface area are obtained. The method is simple and the metal nano particles with uniform particle size are obtained by this method. | 02-05-2009 |
20090131247 | HIGHLY DISPERSED CARBON SUPPORTED METAL CATALYST AND METHOD FOR MANUFACTURING THE SAME - The invention provides a method for manufacturing a highly dispersed carbon supported metal catalyst, including charging a carbon support and a dispersing agent in water. The carbon support is evenly dispersed in water with an average diameter of 10 nm to 2000 nm and a specific surface area of 50 m | 05-21-2009 |
20130029252 | FUEL CELL AND ELECTROCATALYST - An embodiment of the invention provides an electrocatalyst, including a four-element catalyst having a formula of XYZP, wherein X is Pt or Pd, Y and Z are different elements selected from Group 6, Group 8, Group 9, or Group 11 elements, and P is phosphorous, wherein Group 6 elements include Cr, Mo, or W, Group 8 elements include Fe, Ru, or Os, Group 9 elements include Co, Rh, or Ir, and Group 11 elements include Cu, Ag, or Au. | 01-31-2013 |
Ming-Shan Lo, Hsinchu City TW
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20150091073 | NONVOLATILE MEMORY STRUCTURE AND FABRICATION METHOD THEREOF - According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer. | 04-02-2015 |
20160079251 | SINGLE-POLY NONVOLATILE MEMORY CELL - A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer. | 03-17-2016 |
Min Ming Lo, Hsinchu City TW
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20090237098 | WAFER TESTING SYSTEM INTEGRATED WITH RFID TECHNIQUES AND THESTING METHOD THEREOF - This invention provides a wafer testing system and testing method thereof. The wafer testing system comprises a wafer storage section, a prober, a tester, an RFID middleware unit, an EDA system and an MES system. The wafer storage section stores a multiplicity of carriers, each of which is provided with at least a RFID tag. The prober comprises a RFID reader to read a tag information. The tester sends a test signal to the prober for implementing the wafer test so as to generate a test result and calls an interface program to convert the test result into a file conformed with a specific data format. The RFID middleware unit receives the tag information and calls related applications to process the tag information so as to generate a wafer information. The EDA system receives the file of the specific data format converted from the interface program and calculates thereof to generate a wafer yield information after wafer test. The MES system integrates the wafer information from the RFID middleware unit with the yield information from the EDA system so as to allow monitoring the wafer manufacturing process and testing yield rate in a real-time manner. | 09-24-2009 |
Pang-Ping Lo, Hsinchu City TW
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20150176153 | GAS-SUPPLY SYSTEM AND METHOD - A gas-supply system includes a gas container filled with gas, a gas flow controller coupled to the gas container via a first tube, and an operation device electrically connected to the gas flow controller. The gas-supply system further includes a pressure transducer installed on a second tube connected to the gas flow controller and configured to generate a pressure signal to the operation device according to the pressure of the gas in the second tube. The operation device is configured to generate a control signal to the gas flow controller according the pressure signal, and the gas flow controller is configured to adjust the flow rate of the gas in the second tube according to the control signal. | 06-25-2015 |
Pei-Ting Lo, Hsinchu City TW
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20130312813 | SOLAR CELL AND MODULE THEREOF - A solar cell includes a silicon semiconductor substrate, a composite multifunctional protective film, a plurality of front electrodes and a plurality of back electrodes. The silicon semiconductor substrate has a roughened first surface. A depth of the doped layer arranged under the first surface ranges from 200 nm to 1000 nm. A surface doping concentration of the doped layer ranges from 1×10 | 11-28-2013 |
Sheng-Chung Lo, Hsinchu City TW
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20140130911 | ENERGY CAPTURING SYSTEM AND PRESSURE STABILIZING DEVICE THEREOF - An energy capturing system includes a first chamber, a second chamber, a spacer element, a pressurization device, an energy capturing device and a pressure stabilizing device. The first chamber and the second chamber are adapted to contain a liquid. The spacer element is located between the first chamber and the second chamber. The second chamber is connected with the first chamber via an opening of the spacer element. Two ends of the pressurization device are connected with the first chamber and the second chamber, respectively. The energy capturing device is located on the opening. The pressure stabilizing device is connected with the first chamber. | 05-15-2014 |
Shen-Min Lo, Hsinchu City TW
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20100052591 | MOTOR DRIVING CIRCUIT FOR ADJUSTING SPEED OF A MOTOR BY CHANGING AN OUTPUT VOLTAGE - A motor driving circuit for adjusting speed of the motor by changing output voltage is disclosed. One end of the motor is coupled to a variable voltage source. The motor driving circuit includes a motor-driving unit, a control unit and a determining unit. The motor-driving unit includes a first end coupled to another end of the motor, a second end coupled to a ground and a third end, and is utilized for driving the motor. The control unit is utilized for controlling the voltage between the first end and the third end of the motor-driving unit. The determining unit is coupled between the variable voltage source and the control unit, and is utilized for controlling the control unit to adjust the voltage between the first end and the third end of the motor-driving unit according to magnitude of the voltage of the variable voltage source. | 03-04-2010 |
20100054964 | Rotating Speed Adjustment Circuit and Related Control System for a Heat Dissipation Fan - A rotating speed adjustment circuit for a heat dissipation fan includes a first node, a second node, a reception end for receiving a first control signal, a first resistor coupled to a voltage source and the first node, a second resistor coupled to the first node and the second node, a third resistor coupled to the second node and a ground end, a capacitor coupled to the first node and the ground end, a transistor coupled to the reception end, the second node and the ground end, an oscillator for generating an oscillating signal, and a comparator for comparing a signal of the first node and the oscillating signal, so as to output a second control signal to control a rotating speed of the heat dissipation fan. | 03-04-2010 |
Shih-Ming Lo, Hsinchu City TW
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20120135836 | HYBRID VEHICLE AND HYBRID POWER SYSTEM - An operation method of a hybrid vehicle having an automatic manual transmission system adapted to use at least two energy sources is provided with the following steps. Engaging an engine with a starter generator motor such that the engine and the starter generator motor rotate synchronously. Performing a speed changing by using a control unit assembly through controlling rotation speed of the traction motor and a rotation speed of the starter generator motor to a desired rotation speed for the speed changing according to a running state of the vehicle, such that the engine and the traction motor nearly rotate synchronously with the automatic manual transmission system to perform a gear ratio shifting process thereby to perform the speed changing. Controlling an automatic-switching clutch to engage or disengage the engine and the traction motor to achieve a plurality of driving mode for the vehicle. | 05-31-2012 |
20130140920 | STATOR ASSEMBLY STRUCTURE FOR AXIAL FLUX ELECTRIC MACHINE - A stator assembly structure for an axial flux electric machine is designed. The back iron for each silicon steel disk stator is formed into a specific structure with tooth-like protrusions for allowing the same to be integrated with the disk-type stator seat, while the disk-type stator seat is made of a material suitable for casting or mold forming. A coil is mounted on the disk stator, and a stator assembly is achieved by integrating the stator, the coil and the stator seat. The stator and the disk-type stator seat of the stator assembly are manufactured by using a one-piece cast or one-piece mold forming method so as to enable the contact surfaces of the stator and the stator seat to engage with each other even more tightly, and consequently enable the heat generated from the coil to be transmitted rapidly from the disk stator to the disk-type stator seat. | 06-06-2013 |
Shi-Wei Lo, Hsinchu City TW
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20160042532 | METHOD FOR MONITORING WATER LEVEL OF A WATER BODY AND SYSTEM FOR IMPLEMENTING THE METHOD - In a method for monitoring water level of a water body, a monitoring system is configured to: capture a current image that has a portion of the water body, and a remaining portion aside from the portion of the water body; process the current image into a processed image that includes a water body region corresponding to the portion of the water body, and a background region corresponding to the remaining portion of the current image; mark, on the processed image, a plurality of virtual alert points according to a predetermined water level of the water body; determine whether at least one of the virtual alert points is located within the water body region of the processed image; and generate a monitoring result according to the determination thus made. | 02-11-2016 |
Shun-Chang Lo, Hsinchu City TW
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20120072151 | ENERGY DETECTION METHOD AND AN ENERGY DETECTION CIRCUIT USING THE SAME - An energy detection method is provided. The method obtains an initial time point of an input signal with reference to a digital signal corresponding to the input signal. An i | 03-22-2012 |
Su-Chueh Lo, Hsinchu City TW
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20110128791 | Method and Apparatus of Performing an Erase Operation on a Memory Integrated Circuit - Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines. | 06-02-2011 |
20110317493 | Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit - Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. | 12-29-2011 |
20120092940 | Memory Device and Read Operation Method Thereof - A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current. | 04-19-2012 |
20120262987 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state. | 10-18-2012 |
20120262988 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block. | 10-18-2012 |
20120300553 | Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit - Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. | 11-29-2012 |
20130027120 | Standby Charge Pump System - In one aspect, a charge pump output of a charge pump is coupled to a capacitor of a voltage shifter. The output of the voltage shifter causes pump control logic to enable the charge pump. In another aspect, a transistor in saturation has a drain terminal coupled to a charge pump output and a source terminal coupled to an output mode providing a word line read voltage. | 01-31-2013 |
20130100745 | Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit - Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines. | 04-25-2013 |
20140210522 | DRIVE CIRCUITRY COMPENSATED FOR MANUFACTURING AND ENVIRONMENTAL VARIATION - Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process. | 07-31-2014 |
20140219026 | METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS - Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state. | 08-07-2014 |
20140269125 | Device and Method for Improving Reading Speed of Memory - A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers. | 09-18-2014 |
20150023120 | MEMORY DEVICE AND READ OPERATION METHOD THEREOF - A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged. | 01-22-2015 |
20150206557 | DEVICE AND METHOD FOR IMPROVING READING SPEED OF MEMORY - A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers. | 07-23-2015 |
20150220390 | PROGRAMMING METHOD, READING METHOD AND OPERATING SYSTEM FOR MEMORY - A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1. | 08-06-2015 |
20160041861 | METHOD AND DEVICE FOR MONITORING DATA ERROR STATUS IN A MEMORY - A method for monitoring data error status of a memory device includes generating, by a memory controller, a data status indication code indicating error status of a data chunk transmitted by the memory controller and outputting, by the memory controller, the data status indication code to a user interface. | 02-11-2016 |
20160072486 | SENSE AMPLIFIER WITH IMPROVED MARGIN - One aspect of the technology is an integrated circuit, comprising a bias circuit and a sense amplifier. The bias circuit has a diode-connected transistor and a first bias voltage. The first bias voltage is represented by a first term inversely dependent on a first mobility of charge carriers of the diode-connected transistor and inversely dependent on a first gate-to-channel dielectric capacitance of the diode-connected transistor. The sense amplifier is coupled to another transistor that has a gate coupled to the first bias voltage of the bias circuit. | 03-10-2016 |
Tseng Chin Lo, Hsinchu City TW
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20080244475 | Network based integrated circuit testline generator - A network based integrated circuit testline generating system and method of using the same is described. The system includes a user interface for generating and submitting requests which specify types and configurations of needed testlines for device parametric test. A testline generator receives the requests and creates a layout data base which includes layout information of needed testlines. | 10-02-2008 |
20130335109 | METHOD OF TEST PROBE ALIGNMENT CONTROL - A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value. | 12-19-2013 |
20150192616 | Method of Test Probe Alignment Control - A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value. | 07-09-2015 |
20150268271 | MULTIDIRECTIONAL SEMICONDUCTOR ARRANGEMENT TESTING - One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements. | 09-24-2015 |
Tzu-Jen Lo, Hsinchu City TW
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20120319967 | SINGLE FPC BOARD FOR CONNECTING MULTIPLE MODULES AND TOUCH SENSITIVE DISPLAY MODULE USING THE SAME - A single flexible printed circuit (FPC) board for connecting multiple modules including a thin film is provided. The thin film has a first module connecting portion, a second module connecting portion and a third module connecting portion. The first module connecting portion is located on a first side of the thin film. The second module connecting portion and the third module connecting portion are located on a second side of the thin film. The first side is opposite to the second side. At least one first line is disposed between the first module connecting portion and the second module connecting portion. At least one second line is disposed between the first module connecting portion and the third module connecting portion. | 12-20-2012 |
20150022744 | SINGLE FPC BOARD FOR CONNECTING MULTIPLE MODULES AND TOUCH SENSITIVE DISPLAY MODULE USING THE SAME - A single flexible printed circuit (FPC) board for connecting multiple modules including a thin film is provided. The thin film has a first module connecting portion, a second module connecting portion and a third module connecting portion. The first module connecting portion is located on a first side of the thin film. The second module connecting portion and the third module connecting portion are located on a second side of the thin film. The first side is opposite to the second side. At least one first line is disposed between the first module connecting portion and the second module connecting portion. At least one second line is disposed between the first module connecting portion and the third module connecting portion. | 01-22-2015 |
Wan-Yu Lo, Hsinchu City TW
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20140014945 | PIXEL STRUCTURE AND METHOD OF MANUFACTURING A PIXEL STRUCTURE - A pixel structure and a method of manufacturing a pixel structure are provided. The pixel structure includes an active device, a gate insulation layer, a dielectric insulation layer, a capacitance electrode, a protection layer and a pixel electrode. The active device includes a gate, a semiconductor channel layer, a source and a drain. The dielectric insulation layer covers the semiconductor channel layer. A dielectric index of the dielectric insulation layer is greater than a dielectric index of the gate insulation layer. The capacitance electrode is overlapped with the drain. The capacitance electrode, the drain and the dielectric insulation layer between the two constitute a storage capacitor structure. The protection layer is disposed on the dielectric insulation layer and the capacitance electrode is located between the protection layer and the dielectric insulation layer. The pixel electrode is disposed on the protection layer and connected to the drain of the active device. | 01-16-2014 |
Wei-Jen Lo, Hsinchu City TW
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20100128172 | Apparatus and method for motion adaptive deinterlacing - An apparatus and method for motion adaptive deinterlacing is provided. The apparatus includes a motion average unit, a check area defining unit, and a combing check unit. The motion average unit is configured to obtain a weighted mean motion of a target pixel by performing weighted mean for motions of the target pixel and a plurality of neighboring pixels according to similarity of the target pixel and the neighboring pixels. The check area defining unit is configured to search for a specific check area according to the weighted mean motion. The combing check unit is configured to check combing of the specific check area for a deinterlacing format determining unit to determine a deinterlacing method for the pixels within the specific check area. | 05-27-2010 |
20100128173 | APPARATUS AND METHOD FOR MOTION ADAPTIVE DEINTERLACING - An apparatus and method for motion adaptive deinterlacing are provided. According to the method, a mean motion of a target pixel is obtained according to the target pixel and multiple neighboring pixels. A specific check area is obtained by setting the target pixel as a center and extending toward both sides of a first direction when the mean motion is higher than a first threshold value. The specific check area stops extending in reaching a pixel with a motion lower than a second threshold value. The second threshold value is lower than the first threshold value. The specific check area stops extending on a tail side of the first direction by reaching a first specific number of pixels from the target pixel. Combing of the specific check area is checked to determine a deinterlacing method for pixels within the specific check area. | 05-27-2010 |
20100315556 | IMAGE PROCESSING CIRCUIT AND METHOD THEREOF - An image processing circuit and a method thereof are provided herein. The image processing circuit has a first scaling circuit, a plurality of line buffers, a first sharpness circuit, a second scaling circuit, and a second sharpness circuit. The first scaling circuit enlarges an input image along a first direction to generate a first enlarged image. The line buffers temporarily store the pixel values of a plurality of pixel rows of the first enlarged image. The first sharpness circuit vertically sharpens the first enlarged image to generate a first sharpened image. The second scaling circuit enlarges the first sharpened image along a second direction to generate a second enlarged image. The second sharpness circuit horizontally sharpens the second enlarged image to generate a second sharpened image. Accordingly, it is possible to use the line buffers having shorter data lengths to perform the vertical sharpening. | 12-16-2010 |
20140028919 | IMAGE PROCESSING CIRCUIT AND METHOD THEREOF - An image processing circuit and a method thereof are provided herein. The image processing circuit has a first scaling circuit, one or more line buffers, a first sharpness circuit, a second scaling circuit, and a second sharpness circuit. The first scaling circuit enlarges an input image along a first direction to generate a first enlarged image. The one or more line buffers temporarily store the pixel values of a plurality of pixel rows of the first enlarged image. The first sharpness circuit vertically sharpens the first enlarged image to generate a first sharpened image. The second scaling circuit enlarges the first sharpened image along a second direction to generate a second enlarged image. The second sharpness circuit horizontally sharpens the second enlarged image to generate a second sharpened image. Accordingly, it is possible to use the one or more line buffers having shorter data lengths to perform the vertical sharpening. | 01-30-2014 |
20140333838 | IMAGE PROCESSING METHOD - An image processing method for processing an input image is provided. The image processing method includes: performing a plurality of first imaging processing operations on the input image to generate a first image; and performing a plurality of second imaging processing operations on the first image. Each of the first imaging processing operations is along a first direction, and the plurality of first imaging processing operations include a first scaling operation for increasing resolution. Each of the second imaging processing operations is along a second direction different from the first direction, and the plurality of second imaging processing operations include a second scaling operation for increasing resolution. | 11-13-2014 |
20150333900 | Clock Generating Device and Related Synchronization Method - A clock generating device is disclosed. The clock generating device includes a clock generating unit, for counting a synchronization period of a synchronization signal, generating a first interrupt signal according to the synchronization signal, generating a pulse-width modulation signal according a control signal, counting a phase difference between the synchronization signal and the pulse-width modulation signal, and generating a second interrupt signal according to the pulse-width modulation signal; and a computing unit, for acquiring the synchronization period according to the first interrupt signal, acquiring the phase difference according to the second interrupt signal, and adjusting the control signal according to the synchronization period, a modulation period of the pulse-width modulation signal and the phase difference. | 11-19-2015 |
Wen-Chih Lo, Hsinchu City TW
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20130207903 | TOUCH PANEL - A touch panel, adapted for a touch control apparatus with a display unit, is disclosed, which comprises: a protection plate, having a covering area and a transparent area formed on a surface thereof; a touch sensitive layer, arranged between the protection plate and the display unit at a position corresponding to the transparent area; a conductive circuit, arranged between the protection plate and the display unit at a position corresponding to the transparent area while being electrically connected to the touch sensitive layer. In addition to the expected touch control functions, the touch panel of the invention can enable more icons to be displayed on the display unit. | 08-15-2013 |
Wen-Chung Lo, Hsinchu City TW
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20090059313 | SHEET FEEDING MECHANISM WITH DUPLEX PRINT FUNCTION AND RELATED PRINTER - A sheet feeding mechanism having a pickup roller, a switch device, and a gear set is disclosed. The pickup roller drives a recording material to a first path, and the recording material proceeds from the first path to a second path or from a third path to a fourth path when the switch device is switched to a first position, and proceeds from the first path to the third path when the switch device is switched to a second position. The gear set drives the recording material from the first path to the third path when the switch device is switched to the second position and drives the recording material from the first path to the second path, from the third path to the fourth path, and from the fourth path to the first path when the switch device is switched to the first position. | 03-05-2009 |
20090289413 | SHEET EJECTION MECHANISM AND DUPLEX SHEET FEEDING SYSTEM HAVING THE SGEEET EJECTION MECHANISM - A sheet ejection mechanism including a sheet ejection roller capable of rotating along a selective direction and having an arc portion and a plane portion, the arc portion and the plane portion forming a D-shape cross-section, and a pinch member configured at a position adjacent to the sheet ejection roller, wherein a recording medium is clamped and conveyed between the pinch member and the arc portion of the sheet ejection roller, and a gap is formed between the plane portion and the pinch member for allowing the recording medium to pass. Also, the present invention provides a duplex sheet feeding system having the sheet ejection mechanism. | 11-26-2009 |
Yen Kuo Lo, Hsinchu City TW
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20080225034 | Image sticking erasing circuit and method for using the same - The image sticking erasing circuit includes a detection circuit and a switching circuit connected to the detection circuit. The detection circuit is for use in detecting a first voltage signal, which closely follows the variation of the voltage source, and a reference voltage, which loosely follows the variation of the voltage source. When the detection circuit determines that the first voltage signal is lower than a first threshold value, the switching circuit switches the gate of a driving transistor to a second voltage signal, which loosely follows the voltage source. When the detection circuit determines that the reference voltage signal is lower than a second threshold value, the switching circuit switches the gate of a driving transistor to a low voltage state. | 09-18-2008 |
Yi-Ling Lo, Hsinchu City TW
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20120097544 | CARRIER-ATTACHED COPPER FOIL AND METHOD FOR MANUFACTURING THE SAME - In an embodiment of the invention, a method for manufacturing a carrier-attached copper foil is provided. The method includes providing a carrier foil including stainless steel, titanium, aluminum, nickel or alloy thereof with a surface oxide layer, and forming a copper foil onto the carrier foil to prepare the carrier-attached copper foil. | 04-26-2012 |
20120241082 | FABRICATING METHOD OF FLEXIBLE CIRCUIT BOARD - A fabricating method of a flexible circuit board includes the following steps. The metal carrier foil with metal oxide layer on its surfaces is provided first. The metal oxide layer is formed from the spontaneous oxidization of the metal carrier foil in ambient air and provides passive protection in a sulfuric acid solution or an acidic copper sulphate solution. A conductive seed layer is electroplated onto the metal oxide layer. A flexible insulating layer is formed onto the conductive seed layer by performing a polyimide casting process. The metal carrier foil is then peeled off from the conductive seed layer, which is supported by the insulating layer. A patterned circuit is formed on the insulating layer by performing photoresist coating, developing and etching. | 09-27-2012 |
Ying-Che Lo, Hsinchu City TW
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20090061933 | Multiple Interface Card In A Mobile Phone - A multiple interface smart card adaptor is described for mobile phones to take advantage of at least wireless and contactless communications. | 03-05-2009 |
20110080339 | Motion Sensitive Gesture Device - A wireless wrist mouse, used with an apparatus including a display having a cursor, has a body mountable to a user's hand/wrist by wrist mounting structure. A motion sensor and motion circuitry are carried by the body and are operably connected to one another. The motion circuitry includes a library of command motions. The motion circuitry is constructed to generate first and second command signals corresponding to the first and second command motions when the body has been moved in predetermined manners for receipt by and operation of the apparatus. The first command signals correspond to cursor movement directions for controlling movement of the cursor over the display. The second command signals correspond to control functions for the apparatus. In some examples, the motion sensor comprises a MEMS sensor. In some examples, the motion sensor comprises a translational, rotational, and vibrational movement motion sensor. | 04-07-2011 |
20120022957 | System and Method of Managing Contactless Payment Transactions Using a Mobile Communication Device as a Stored Value Device - A method handling payment transactions in a system using mobile communication devices as stored value devices is disclosed. A transaction operations server receives multiple records of the transaction from the stored value device—one via a communication channel through the telecommunication provider network, and another via an independent communication channel. The records are reconciled at the transaction server for transaction verification. | 01-26-2012 |
20120058722 | MULTIPLE INTERFACE CARD - A multiple interface smart card adaptor is described for mobile phones to take advantage of at least wireless and contactless communications. | 03-08-2012 |
20130204560 | Gas Gauge Device - The present invention discloses a gas gauge device for measuring a state of charge of a battery. The gas gauge device comprises a first programmable gain amplifier (PGA), for amplifying a battery current of the battery with a first adjustable gain, to generate an amplified battery current; a first analog to digital (ADC) converter, for converting the amplified battery current into a digital amplified battery current with a first adjustable sampling rate; and a micro controller, for adjusting the first adjustable gain and the first adjustable sampling rate to measure the battery current. | 08-08-2013 |
Yi-Yang Lo, Hsinchu City TW
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20130142357 | METHOD FOR VISUALIZING SOUND SOURCE ENERGY DISTRIBUTION IN ECHOIC ENVIRONMENT - A method for visualizing sound source energy distribution in an echoic environment comprises steps: arranging in an echoic environment a plurality of arrayed sound pickup units, wherein each sound pickup unit includes at least two microphones separated by a directive distance enabling the sound pickup unit to have a primary pickup direction; disposing the sound pickup units with the primary pickup directions thereof pointing toward a sound source in the echoic environment, and measuring the sound source by the sound pickup units to obtain a sound source-related parameter; substituting the directive distance and the parameter into an algorithm to make the parameter have directivity; and then substituting the parameter into an ESM algorithm to establish a sound source energy distribution profile. Thereby, the method can measure a sound source in a specified direction in an echoic environment and establish a visualized sound source energy distribution profile. | 06-06-2013 |
20130329907 | MINITURE ELECTRONIC SHOTGUN MICROPHONE - A miniature electronic shotgun microphone, which is used to receive a sound source from a specified direction, comprises a pick-up member, an A/D (Analog/Digital) conversion unit, and a digital signal processor. The pick-up member includes a first pick-up unit, a second pick-up unit separated from the first pick-up unit by a first distance, and a third pick-up unit separated from the second pick-up unit by a second distance; the first distance is greater than the second distance. The first pick-up unit, the second pick-up unit and the third pick-up unit respectively receive the sound source and output an analog signal. The A/D conversion unit and the digital signal processor process the analog signals, and convert them into a directional digital acoustic signal. Thus, the directional digital acoustic signal has a maximum pick-up frequency. Thereby is decreased grating lobes and spatial aliasing. | 12-12-2013 |
20150117697 | AUDIO PLAYBACK DEVICE - An audio playback device is provided. The audio playback device includes a magnetic module, an annular armature, a coil module and a diaphragm. The magnetic module includes a magnetic source and two yokes each connected to one of two magnetic poles generated by the magnetic source and extends to form a magnetic field. The annular armature includes a first, a second, a third and a fourth arms that form a hollow area. At least part of the first arm is located in the magnetic area. The coil module is winded on the second arm and generates two varying electro-magnetic poles according to an alternating current data signal. The annular armature vibrates according to a relation of the two varying electro-magnetic poles and the magnetic field. The diaphragm is connected to the annular armature through a driving rod to vibrate according to the annular armature to generate a sound wave. | 04-30-2015 |
Yu-Lan Lo, Hsinchu City TW
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20110296365 | EXTRACTING METHODS FOR CIRCUIT MODELS - The present invention relates to an extracting method for a circuit model, configured to represent output driving capability and an input capacitor of an interface pin of an application circuit. The extracting method comprises: receiving a netlist describing a circuit structure of the application circuit, which comprises a plurality of transistors; selecting an interface pin of the application circuit in the netlist; selecting a bias pin of the application circuit in the netlist; selecting at least one path between the interface pin and the bias pin in the netlist; and obtaining sum of equivalent width/length ratios according to the width/length ratios of all first transistors coupled to the at least one path. | 12-01-2011 |