Patent application number | Description | Published |
20090283847 | SEMICONDUCTOR PACKAGE INCLUDING THROUGH-HOLE ELECTRODE AND LIGHT-TRANSMITTING SUBSTRATE - An imaging element is formed on the first main surface of a semiconductor substrate. An external terminal is formed on the second main surface of the semiconductor substrate. A through-hole electrode is formed in a through hole formed in the semiconductor substrate. A first electrode pad is formed on the through-hole electrode in the first main surface. An interlayer insulating film is formed on the first electrode pad and on the first main surface. A second electrode pad is formed on the interlayer insulating film. A passivation film is formed on the second electrode pad and the interlayer insulating film, and has an opening which exposes a portion of the second electrode pad. A contact plug is formed between the first and second electrode pads in a region which does not overlap the opening when viewed in a direction perpendicular to the surface of the semiconductor substrate. | 11-19-2009 |
20090284631 | SEMICONDUCTOR PACKAGE AND CAMERA MODULE - A semiconductor package includes a solid-state imaging element, electrode pad, through-hole electrode, and light-transmitting substrate. The solid-state imaging element is formed on the first main surface of a semiconductor substrate. The electrode pad is formed on the first main surface of the semiconductor substrate. The through-hole electrode is formed to extend through the semiconductor substrate between the first main surface and a second main surface opposite to the electrode pad formed on the first main surface. The light-transmitting substrate is placed on a patterned adhesive to form a hollow on the solid-state imaging element. The thickness of the semiconductor substrate below the hollow when viewed from the light-transmitting substrate is larger than that of the semiconductor substrate below the adhesive. | 11-19-2009 |
20110068476 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad. | 03-24-2011 |
20120008934 | CAMERA MODULE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a camera module is disclosed. The module includes a semiconductor substrate having a first main surface and a second main surface facing the first main surface. An imaging region is provided on the first main surface. A penetrative electrode penetrates through the semiconductor substrate between the first main surface and the second main surface. An adhesive layer is provided on the first main surface, the adhesive layer being located outside the imaging region. And a lens member is directly bonded to the adhesive layer, the lens member seals the imaging region and houses an imaging lens therein. | 01-12-2012 |
20120068291 | IMAGE SENSING DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a solid-state image sensing device includes a semiconductor substrate on which a plurality of pixels are arranged, a transparent substrate including a first through via provided in an opening formed in advance to extend through, an adhesive including a second through via connected to the first through via and configured to bond the semiconductor substrate and the transparent substrate while exposing the pixels, and an imaging lens unit arranged on the transparent substrate. | 03-22-2012 |
Patent application number | Description | Published |
20120241846 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction. | 09-27-2012 |
20130020627 | SHIFT REGISTER MEMORY AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction. | 01-24-2013 |
Patent application number | Description | Published |
20090059247 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD THEREOF - There is provided an image processing apparatus that generates print data for printing by an inkjet printing apparatus, based on a rendering command group that includes a rendering command for a vector image, comprising: a determination unit which determines, for each rendering command included in the rendering command group, whether ink having a predetermined property is to be used; a rendering unit which renders in a first memory a raster image corresponding to a rendering command for ink having the predetermined property is to be used, and renders in a second memory a raster image corresponding to a rendering command for ink having the predetermined property is not to be used; a lossy compression unit which lossily compresses the raster image in the first memory; and a generation unit which generates print data that includes the raster image in the first memory and the raster image in the second memory. | 03-05-2009 |
20100020356 | PRINTING CONTROL APPARATUS AND METHOD THEREOF - Print commands are saved in increments of pages, based on usable storage capacity, at the time of printing processing of a first copy, so that page spacing to save the print commands is as uniform as possible. At the time of printing processing of the second copy, the stored print commands are reused and transferred to a printer, and the print commands not stored are generated again. The transferring and generating of the print commands are performed in parallel. | 01-28-2010 |
20100165399 | JOB STATUS MONITORING SYSTEM, JOB STATUS MONITORING METHOD, PROGRAM, AND STORAGE MEDIUM - A job status monitoring system includes a job output unit configured to output a job to a job managing unit of an operating system. The job is issued in response to a job issue request. A status of the job output to a printer is monitored by a monitoring unit. The monitoring unit controls the job managing unit by monitoring the status of the job. An application or utility determines the status of the job by obtaining information about the job from the job managing unit and performs display control based on the determined status of the job. | 07-01-2010 |
20100302593 | PRINTING CONTROL APPARATUS, PRINTING CONTROL METHOD, AND COMPUTER-READABLE STORAGE MEDIUM STORING PROGRAM - A printing control apparatus confirms whether a predetermined free space is present to stabilize an operation of a system. If it is determined that the predetermined free space is not present, the printing control apparatus deletes at least a part of stored print data. In a case where the predetermined free space becomes available by preliminarily performed deletion processing, the printing control apparatus stores print data of a first copy. Then, in the print processing for second and subsequent copies, if print data of a target page is already present, the printing control apparatus skips the processing for generating the print data of the target page. | 12-02-2010 |
20140362405 | INFORMATION PROCESSING APPARATUS, RECORDING MEDIUM, AND CONTROL METHOD - There is provided an information processing apparatus including a first filter configured to merge first print setting information of a first hierarchical level and second print setting information of a second hierarchical level to generate and store third print setting information, wherein the second hierarchical level is lower than the first hierarchical level; and a second filter subsequent to the first filter configured to acquire the third print setting information stored in the first filter. | 12-11-2014 |
Patent application number | Description | Published |
20090063086 | APPARATUS FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for testing a semiconductor integrated circuit includes an input part that inputs circuit description data that describes a circuit structure of the semiconductor integrated circuit, a clock domain of the semiconductor integrated circuit, and a first test vector to be used for testing a normal operation of the semiconductor integrated circuit, and a simulator that performs a simulation on the semiconductor integrated circuit with the use of a test vector. The simulator includes an asynchronous transfer point extraction unit that extracts an asynchronous transfer point in the semiconductor integrated circuit in accordance with the circuit description data and the clock domain that are input through the input part, a simulation unit that calculates a logic circuit output of the semiconductor integrated circuit by performing a simulation in accordance with the circuit description data and the first test vector that are input through the input part, and a second test vector generation unit that generates a second test vector by changing a signal of an asynchronous transfer point of the logic circuit output calculated by the simulation unit in accordance with the asynchronous transfer point extracted by the asynchronous transfer point extraction unit. | 03-05-2009 |
20100306725 | APPARATUS AND METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER READABLE MEDIUM - An apparatus for designing a semiconductor integrated circuit according to an embodiment of the present invention includes an interface circuit information extracting unit configured to specify one or more transmitting registers and one or more receiving registers forming an interface that needs to be synchronized, an insertion point candidate specifying unit configured to specify a number of supply sources that is of a number of the transmitting registers serving as data supply sources, for each receiving register, and specify at least one insertion point candidate based on the number of supply sources, an insertion point specifying unit configured to specify a number of output destinations that is of a number of the receiving registers serving as data output destinations, for each transmitting register, and specify at least one insertion point based on the number of output destinations and the insertion point candidate, and a synchronization circuit inserting unit configured to insert a synchronization circuit in the insertion point, and generate synchronized circuit description data of the semiconductor integrated circuit in which the synchronization circuit is inserted in the insertion point. | 12-02-2010 |