Patent application number | Description | Published |
20100198768 | SYSTEM AND METHODS FOR OPTIMIZING USER INTERACTION IN WEB-RELATED ACTIVITIES - A method and apparatus is disclosed herein for facilitating user interaction in web-related activities. In one embodiment, the method comprises monitoring a user's current interaction with a browser, predicting a task a user is likely to take based on a current interaction context associated with the user's current interaction and one or more rules previously generated based on one or more previously recorded browser interactions, and generating, based on the prediction, and displaying a user interface component with the browser, the user interface component selectable by the user and representing an interaction (or a sequence of interactions) that the user can select to occur. | 08-05-2010 |
20130278622 | Secure and Authenticated Transactions with Mobile Devices - Embodiments of the invention include a platform for using 2D barcodes to establish secure authenticated communication between two computing devices that are in proximity to each other. A two-tier application architecture using a single base app and dynamic add-on applets is used. 2D barcodes can be distinctively visually branded. According to other aspects, the security of mobile payment systems are enhanced by (1) a triangular payment settlement in which the sender and receiver of payment each submit transaction information independently to the same payment server; (2) sensitive information is split into two parts, one of which is stored on a mobile device, and the other of which is stored on a payment server, and the two parts are only combined and exist transiently in the payment server's volatile memory when executing a transaction; and (3) a process to securely update profile pictures associated with payment accounts. | 10-24-2013 |
20130342459 | FINGERTIP LOCATION FOR GESTURE INPUT - A user can use a finger, or other such object, to provide input to a computing device. The finger does not have to contact the device, but can be positioned and/or oriented in such a way that the device can determine an input that the user is attempting to provide, such as an element or icon that the user is intended to select. One or more cameras can capture image information, which can be analyzed to attempt to determine the location and/or orientation of the finger. If the finger is at least partially outside a field of view of the camera(s), the device can use a sensor (e.g., EMF) to attempt to determine a location of at least a portion of the finger, which can be used with the image information to determine the location and/or orientation of the finger. Other estimation processes can be used as well. | 12-26-2013 |
20140282269 | NON-OCCLUDED DISPLAY FOR HOVER INTERACTIONS - A computing device can be configured to recognize when a user hovers over or is within a determined distance of an element displayed on the computing device to perform certain tasks. Information associated with the element can be displayed when such a hover input is detected. This information may comprise a description of what tasks are performed by selection of the element. This information could also be an enlarged version of the element to help the user disambiguate selection of multiple elements. The information can be displayed in a manner such that at least substantive portions of the information would not be obscured or occluded by the user. | 09-18-2014 |
20150049017 | GESTURE RECOGNITION FOR DEVICE INPUT - A user can make a symbol with their hand, or other such gesture, at a distance from a computing device that can be captured by at least one imaging element of the device. The captured information can be analyzed to attempt to determine the location of distinguishing features of the symbol in the image information. The image information is then compared to hand gesture information stored in, for example, a library of hand gestures for the user. Upon identifying a match, an input to an application executing on the computing device is provided when the image information contains information matching at least one hand gesture with at least a minimum level of certainty. The hand gesture could include a single “static” gesture, such as a specific letter in sign language, for example, or include two or more “static” gestures. The gesture could also include motion, such as hand movement. | 02-19-2015 |
20150062006 | FEATURE TRACKING FOR DEVICE INPUT - A user can emulate touch screen events with motions and gestures that the user performs at a distance from a computing device. A user can utilize specific gestures, such as a pinch gesture, to designate portions of motion that are to be interpreted as input, to differentiate from other portions of the motion. A user can then perform actions such as text input by performing motions with the pinch gesture that correspond to words or other selections recognized by a text input program. A camera-based detection approach can be used to recognize the location of features performing the motions and gestures, such as a hand, finger, and/or thumb of the user. | 03-05-2015 |
20150135093 | TRANSFERRING INFORMATION AMONG DEVICES USING SENSORS - Data provided on a first computing device is represented by a graphical object displayed on a screen. A user can initiate an “attach event” with a gesture to enable the graphical object to be associated and/or virtually attached to the user and/or a user's hand/fingers. An image capture component can view/track user movements. Based on the viewed/tracked movements, the graphical object representing the data on the first computing device can be moved on a screen of the first computing device to correspond to the movement of the user's hand/finger. The graphical object also can be moved to a position on a screen of a second computing device when the user moves a hand/fingers to an area corresponding to the position. A user may initiate a “release event” with a gesture and can end the association and enable the data to be sent to the second computing device. | 05-14-2015 |
Patent application number | Description | Published |
20090014127 | SYSTEMS FOR PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION AND BEVEL EDGE ETCHING - Embodiments described herein relate to a substrate processing system that integrates substrate edge processing capabilities. Illustrated examples of the processing system include, without limitations, a factory interface, a loadlock chamber, a transfer chamber, and one or more twin process chambers having two or more processing regions that are isolatable from each other and share a common gas supply and a common exhaust pump. The processing regions in each twin process chamber include separate gas distribution assemblies and RF power sources to provide plasma at selective regions on a substrate surface in each processing region. Each twin process chamber is thereby configured to allow multiple, isolated processes to be performed concurrently on at least two substrates in the processing regions. | 01-15-2009 |
20090017635 | APPARATUS AND METHOD FOR PROCESSING A SUBSTRATE EDGE REGION - The present invention comprises an apparatus and method for etching at a substrate edge region. In one embodiment, the apparatus comprises a chamber having a process volume, a substrate support arranged inside the process volume and having a substrate support surface, a plasma generator coupled to the chamber and configured to supply an etching agent in a plasma phase to a peripheral region of the substrate support surface, and a gas delivery assembly coupled to a gas source for generating a radial gas flow over the substrate support surface from an approximately central region of the substrate support surface toward the peripheral region of the substrate support surface. | 01-15-2009 |
20090044753 | METHODS TO IMPROVE THE IN-FILM DEFECTIVITY OF PECVD AMORPHOUS CARBON FILMS - An article having a protective coating for use in semiconductor applications and methods for making the same are provided. In certain embodiments, a method of coating an aluminum surface of an article utilized in a semiconductor processing chamber is provided. The method comprises providing a processing chamber; placing the article into the processing chamber; flowing a first gas comprising a carbon source into the processing chamber; flowing a second gas comprising a nitrogen source into the processing chamber; forming a plasma in the chamber; and depositing a coating material on the aluminum surface. In certain embodiments, the coating material comprises an amorphous carbon nitrogen containing layer. In certain embodiments, the article comprises a showerhead configured to deliver a gas to the processing chamber. | 02-19-2009 |
20090269512 | NONPLANAR FACEPLATE FOR A PLASMA PROCESSING CHAMBER - A method and apparatus for adjust local plasma density during a plasma process. One embodiment provides an electrode assembly comprising a conductive faceplate having a nonplanar surface. The nonplanar surface is configured to face a substrate during processing and the conductive faceplate is disposed so that the nonplanar surface is opposing a substrate support having an electrode. The conductive faceplate and the substrate support form a plasma volume. The nonplanar surface is configured to adjust electric field between the conductive plate and the electrode by varying a distance between the conductive plate and the electrode. | 10-29-2009 |
20090314208 | PEDESTAL HEATER FOR LOW TEMPERATURE PECVD APPLICATION - A method and apparatus for providing power to a heated support pedestal is provided. In one embodiment, a process kit is described. The process kit includes a hollow shaft made of a conductive material coupled to a substrate support at one end and a base assembly at an opposing end, the base assembly adapted to couple to a power box disposed on a semiconductor processing tool. In one embodiment, the base assembly comprises at least one exposed electrical connector disposed in an insert made of a dielectric material, such as a plastic resin. | 12-24-2009 |
20110034034 | DUAL TEMPERATURE HEATER - A method and apparatus for heating a substrate in a chamber are provided. an apparatus for positioning a substrate in a processing chamber. In one embodiment, the apparatus comprises a substrate support assembly having a support surface adapted to receive the substrate and a plurality of centering members for supporting the substrate at a distance parallel to the support surface and for centering the substrate relative to a reference axis substantially perpendicular to the support surface. The plurality of the centering members are movably disposed along a periphery of the support surface, and each of the plurality of centering members comprises a first end portion for either contacting or supporting a peripheral edge of the substrate. | 02-10-2011 |
20110147363 | MULTIFUNCTIONAL HEATER/CHILLER PEDESTAL FOR WIDE RANGE WAFER TEMPERATURE CONTROL - Embodiments of the invention generally relate to a semiconductor processing chamber and, more specifically, a heated support pedestal for a semiconductor processing chamber. In one embodiment, a pedestal for a semiconductor processing chamber is provided. The pedestal comprises a substrate support comprising a conductive material and having a support surface for receiving a substrate, a resistive heater encapsulated within the substrate support, a hollow shaft coupled to the substrate support at a first end and a mating interface at an opposing end, the hollow shaft comprising a shaft body having a hollow core, and a cooling channel assembly encircling the hollow core and disposed within the shaft body for removing heat from the pedestal via an internal cooling path, wherein the substrate support has a heat control gap positioned between the heating element and the ring-shaped cooling channel. | 06-23-2011 |
20110294303 | CONFINED PROCESS VOLUME PECVD CHAMBER - An apparatus for plasma processing a substrate is provided. The apparatus comprises a processing chamber, a substrate support disposed in the processing chamber, a shield member disposed in the processing chamber below the substrate support, and a lid assembly coupled to the processing chamber. The lid assembly comprises a conductive gas distributor coupled to a power source, and an electrode separated from the conductive gas distributor and the chamber body by electrical insulators. The electrode is also coupled to a source of electric power. The substrate support is formed with a stiffness that permits very little departure from parallelism. The shield member thermally shields a substrate transfer opening in the lower portion of the chamber body. A pumping plenum is located below the substrate support processing position, and is spaced apart therefrom. | 12-01-2011 |
20120204795 | METHODS TO IMPROVE THE IN-FILM DEFECTIVITY OF PECVD AMORPHOUS CARBON FILMS - An article having a protective coating for use in semiconductor applications and methods for making the same are provided. In certain embodiments, a method of coating an aluminum surface of an article utilized in a semiconductor processing chamber is provided. The method comprises providing a processing chamber; placing the article into the processing chamber; flowing a first gas comprising a carbon source into the processing chamber; flowing a second gas comprising a nitrogen source into the processing chamber; forming a plasma in the chamber; and depositing a coating material on the aluminum surface. In certain embodiments, the coating material comprises an amorphous carbon nitrogen containing layer. In certain embodiments, the article comprises a showerhead configured to deliver a gas to the processing chamber. | 08-16-2012 |
20120211164 | SYSTEMS FOR PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION AND BEVEL EDGE ETCHING - Embodiments described herein relate to a substrate processing system that integrates substrate edge processing capabilities. Illustrated examples of the processing system include, without limitations, a factory interface, a loadlock chamber, a transfer chamber, and one or more twin process chambers having two or more processing regions that are isolatable from each other and share a common gas supply and a common exhaust pump. The processing regions in each twin process chamber include separate gas distribution assemblies and RF power sources to provide plasma at selective regions on a substrate surface in each processing region. Each twin process chamber is thereby configured to allow multiple, isolated processes to be performed concurrently on at least two substrates in the processing regions. | 08-23-2012 |
20120211484 | METHODS AND APPARATUS FOR A MULTI-ZONE PEDESTAL HEATER - The present invention provides systems, methods and apparatus for manufacturing a multi-zone pedestal heater. A multi-zone pedestal heater includes a heater plate which includes a first zone including a first heating element and a first thermocouple for sensing the temperature of the first zone wherein the first zone is disposed in the center of the heater plate; and a second zone including a second heating element and a first embedded thermocouple for sensing the temperature of the second zone wherein the first embedded thermocouple includes a first longitudinal piece that extends from a center of the heater plate to the second zone and the first longitudinal piece is entirely encased within the heater plate. Numerous additional aspects are disclosed. | 08-23-2012 |
20120292305 | METHODS AND APPARATUS FOR CONTROLLING TEMPERATURE OF A MULTI-ZONE HEATER IN A PROCESS CHAMBER - Methods and apparatus for controlling the temperature of multi-zone heater in a process chamber are provided herein. In some embodiments, a method is provided to control a multi-zone heater disposed in a substrate support, wherein the multi-zone heater has a first zone and a second zone. In some embodiments, the method may include measuring a current drawn by the first zone at a first time; measuring a voltage drawn by the first zone at the first time; calculating the resistance of the first zone based upon the measured current and voltage drawn by the first zone at the first time; determining a temperature of the first zone based upon a predetermined relationship between the resistance and the temperature of the first zone; and adjusting the temperature of the first zone in response to the temperature determination. | 11-22-2012 |
20130270252 | METHODS AND APPARATUS FOR CONTROLLING TEMPERATURE OF A MULTI-ZONE HEATER IN A PROCESS CHAMBER - Methods and apparatus for controlling the temperature of multi-zone heater in a process chamber are provided herein. In some embodiments, a method is provided to control a multi-zone heater disposed in a substrate support, wherein the multi-zone heater has a first zone and a second zone. In some embodiments, the method may include measuring a current drawn by the first zone at a first time; measuring a voltage drawn by the first zone at the first time; calculating the resistance of the first zone based upon the measured current and voltage drawn by the first zone at the first time; determining a temperature of the first zone based upon a predetermined relationship between the resistance and the temperature of the first zone; and adjusting the temperature of the first zone in response to the temperature determination. | 10-17-2013 |
Patent application number | Description | Published |
20100026270 | AVERAGE INPUT CURRENT LIMIT METHOD AND APPARATUS THEREOF - The embodiment of invention discloses an average input current limit method and apparatus thereof. The apparatus comprises a switching circuit, a current average circuit and a current limit circuit. The current average circuit samples the input current of the switching circuit and generates a signal representative of the average value of the input current. The current limit circuit limits the signal so as to limit the average value of the input current. | 02-04-2010 |
20100110595 | INPUT SURGE PROTECTION DEVICE USING JFET - An input surge suppression device and method that uses a simple JFET structure. The JFET has its gate clamped to a predetermined value, its the drain receives the input voltage from an input power source, its source is connected to the input of a down-stream device, and a resistor connected between the drain and the gate or between the source and the gate. Thus, when the drain voltage approximates the clamped gate voltage, the source voltage nearly equals the drain voltage. When the drain voltage rises above the clamped gate voltage, the source voltage is lower than the drain voltage. The downstream device may be a DC-DC converter and the gate is biased by the enable (EN) pin of a DC-DC converter. | 05-06-2010 |
20110025284 | MULTI-PHASE DC-TO-DC CONVERTER WITH DAISY CHAINED PULSE WIDTH MODULATION GENERATORS - A multi-phase DC-DC converter is disclosed. The DC-DC converter has a plurality of phases, each with a separate PWM generator for driving a totem pole of transistors. A master PWM generator operates off of a master clock signal. The remainder of the phases are slaved to the master PWM generator. | 02-03-2011 |
20120068320 | Integrated Power Converter Package With Die Stacking - An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry. | 03-22-2012 |
20120235652 | SWITCHING MODE POWER SUPPLY WITH VIRTUAL CURRENT SENSING AND ASSOCIATED METHODS - The present technology is related generally to a switching mode power supply with virtual current sensing. The switching mode power supply comprises a power stage that includes a first power switch and a second power switch coupled in series. The switching mode power supply senses a first current flowing through the first power switch during on-time and provides a virtual current sense signal that is proportional to a second current flowing through the second power switch during on-time. The switching mode power supply further combines the real current sense signal and the virtual current sense signal to form a current sense signal, which is sent to the controller to realize desired control. | 09-20-2012 |
20130292814 | INTEGRATED POWER CONVERTER PACKAGE WITH DIE STACKING - An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry. | 11-07-2013 |
20140071720 | VOLTAGE CONVERTER AND ASSOCIATED OVER-VOLTAGE PROTECTION METHOD - A voltage converter includes: an input terminal receiving an input voltage; an output terminal providing an output voltage; a switching circuit having a main switch configured to regulate the output voltage, wherein a control end of the main switch is configured to receive a Pulse Width Modulation (PWM) signal, and the output voltage is controlled according to the duty cycle of the PWM signal; and a protection switch coupled between the input terminal and the switching circuit, and wherein when the output voltage is higher than a reference voltage, the protection switch is turned OFF. | 03-13-2014 |
20150270773 | CONTROL CIRCUIT FOR MULTIPHASE SWITCHING CONVERTER TO REDUCE OVERSHOOT AND ASSOCIATED CONTROL METHOD - A multiphase switching converter having a plurality of switching circuits and a control circuit, the plurality of switching circuits provide an output voltage, the control circuit provides a plurality of switching control signals to turn ON the plurality of switching circuits successively based on the output voltage and a reference signal, when the output voltage is detected overshooting, the control circuit turns OFF a current switching circuit, and when the output voltage is detected recovering from overshooting, the control circuit turns ON the current switching circuit again for a first time period until a sum of the first time period and a second time period achieves a predetermined value, wherein the second time period is a time period the current switching circuit maintains ON uninterruptedly before the output voltage is detected overshooting. | 09-24-2015 |
Patent application number | Description | Published |
20090313296 | METHOD AND APPARATUS FOR MANAGING STORAGE - The invention provides a method and apparatus for managing stored objects. The method includes providing an object management policy for stored objects, analyzing the object management policy to identify information required to execute the object management policy, acquiring the identified information from a protection repository for the stored objects, and executing the object management policy based on the acquired information to manage the stored objects. | 12-17-2009 |
20090313297 | METHOD AND APPARATUS FOR USING SELECTIVE ATTRIBUTE ACQUISITION AND CLAUSE EVALUATION FOR POLICY BASED STORAGE MANAGEMENT - The invention provides a method and apparatus for managing stored data objects. The method includes detecting involved attributes of stored data objects based on object management rules, determining expected data storage management costs for each possible order of attribute acquisition for the detected attributes, detecting an order of attribute acquisition that has a data storage management cost which is minimal or below a predetermined threshold, acquiring the attributes of the stored data objects based on the detected order of attribute acquisition, and executing an object management policy based on the acquired attributes to manage the stored objects at the low cost for object storage, attribute acquisition and policy evaluation. | 12-17-2009 |
20100250501 | STORAGE MANAGEMENT THROUGH ADAPTIVE DEDUPLICATION - One embodiment retrieves a first portion of a plurality of stored objects from at least one storage device. The embodiment further performs a base type deduplication estimation process on the first portion of stored objects. The embodiment still further categorizes the first portion of the plurality of stored objects into deduplication sets based on a deduplication relationship of each object of the plurality of stored objects with each of the estimated first plurality of deduplication chunk portions. The embodiment further combines deduplication sets into broad classes based on deduplication characteristics of the objects in the deduplication sets. The embodiment still further classifies a second portion of the plurality of stored objects into broad classes using classifiers. The embodiment further selects an appropriate deduplication approach for each categorized class. | 09-30-2010 |
20110055621 | DATA REPLICATION BASED ON CAPACITY OPTIMIZATION - A system and associated method for replicating data based on capacity optimization. A local node receives the data associated with a key. The local node within a local domain communicates with nodes of remote domains in a system through a communication network. Each domain has its own distributed hash table that partitions key space and assigns a certain key range to an owner node within the domain. For new data, the local node queries owner nodes of domains in the system progressively from the local domain to remote domains for a duplicate of the new data. Depending on a result returned by owner nodes and factors for replication strategies, the local node determines a replication strategy and records the new data in the local node pursuant to the replication strategy. | 03-03-2011 |
20110138391 | CONTINUOUS OPTIMIZATION OF ARCHIVE MANAGEMENT SCHEDULING BY USE OF INTEGRATED CONTENT-RESOURCE ANALYTIC MODEL - A system and associated method for continuously optimizing data archive management scheduling. A job scheduler receives, from an archive management system, inputs of task information, replica placement data, infrastructure topology data, and resource performance data. The job scheduler models a flow network that represents data content, software programs, physical devices, and communication capacity of the archive management system in various levels of vertices according to the received inputs. An optimal path in the modeled flow network is computed as an initial schedule, and the archive management system performs tasks according to the initial schedule. The operations of scheduled tasks are monitored and the job scheduler produces a new schedule based on feedbacks of the monitored operations and predefined heuristics. | 06-09-2011 |
20110185233 | AUTOMATED SYSTEM PROBLEM DIAGNOSING - Embodiments of the invention relate to automated system problem diagnosing. An index is created with problem description information of previously diagnosed problems, a diagnosis for each problem, and a solution to each diagnosis. System states, traces and logs are extracted from a source system with a new problem. The problem diagnosis system generates problem description information of the new problem from the system states, traces and logs. Problem description information of the new problem is compared with problem description information in the problem description index. A search score is computed for each document in the problem description index. The search score is a measure of similarity between each document in the index and the description of the new problem. A matching score is assigned to each previously diagnosed problems based on the search score. The matching score is a measure of similarity between the new problem and each previously diagnosed problem. The system determines a diagnosis and solution of the new problem based on a diagnosis and solution of one of the previously diagnosed problems. | 07-28-2011 |
20110213508 | OPTIMIZING POWER CONSUMPTION BY DYNAMIC WORKLOAD ADJUSTMENT - A system and associated method for optimizing power consumption of a data center by dynamic workload adjustment. A current workload distribution of the data center is shifted to an optimal workload solution that provides acceptable level of service with the least amount of power consumption. The sum of power cost and migration cost that corresponds to the optimal workload solution is the lowest among all sums that correspond to respective candidate workload solutions. The power cost is determined by a maximum temperature of the data center and accompanying cooling cost for each candidate workload solution. The migration cost is determined by performance degradation that occurs during shifting a workload distribution of the data center from the current workload distribution to each candidate workload solution. | 09-01-2011 |
20110295815 | Proactive Detection of Data Inconsistencies in a Storage System Point-in-Time Copy of Data - Embodiments of the invention relate to testing a storage system point-in-time copy of data for consistency. An aspect of the invention includes receiving system and application event information from systems and applications associated with point-in-time copies of data. The system and application event information is associated with each of point-in-time copies of data. At least one point-in-time copy of data is selected for testing. The system and application event information is compared with inconsistency classes to determine tests for testing the point-in-time copy of data. The point-in-time copy of data is tested. | 12-01-2011 |
20110296237 | SELECTING A DATA RESTORE POINT WITH AN OPTIMAL RECOVERY TIME AND RECOVERY POINT - Embodiments of the invention relate to selecting a data restore point with an optimal recovery time and recovery point. An exemplary embodiment includes generating a problem search criterion for an entity with corrupted data. Dependencies relied on by the entity to function are determined. At least one event signature match is found that comprises information for an event being logged in a event log, and is associated with the dependencies. At least one data restore point created prior to an occurrence of a particular event in the at least one event signature match is selected. The particular event having caused the data to be corrupted. The at least one data restore point is selected to restore data to a storage system with the corrupted data. | 12-01-2011 |
20120304182 | CONTINUOUS OPTIMIZATION OF ARCHIVE MANAGEMENT SCHEDULING BY USE OF INTEGRATED CONTENT-RESOURCE ANALYTIC MODEL - A system and associated method for continuously optimizing data archive management scheduling. A job scheduler receives, from an archive management system, inputs of task information, replica placement data, infrastructure topology data, and resource performance data. The job scheduler models a flow network that represents data content, software programs, physical devices, and communication capacity of the archive management system in various levels of vertices according to the received inputs. An optimal path in the modeled flow network is computed as an initial schedule, and the archive management system performs tasks according to the initial schedule. The operations of scheduled tasks are monitored and the job scheduler produces a new schedule based on feedbacks of the monitored operations and predefined heuristics. | 11-29-2012 |
20120330895 | TRANSITIONING APPLICATION REPLICATION CONFIGURATIONS IN A NETWORKED COMPUTING ENVIRONMENT - Embodiments of the present invention provide an approach for providing non-disruptive transitioning of application replication configurations and proactive analysis of possible error scenarios. Specifically, under embodiments of the present invention, a common integration model (CIM)-compatible representation of a system replication plan is provided in a computer data structure. Based on the representation, a hierarchical tree data structure having a set of nodes is created. A set of system configuration updates pertaining to the set of nodes are then classified (e.g., based upon the type of configuration update). Once the set of nodes has been classified, the set of nodes may then be analyzed to determine if any nodes of the set are isomorphic. If so, the plan can be modified accordingly. In any event, the replication plan (or modified replication plan) may then be implemented. | 12-27-2012 |
20130006943 | HYBRID DATA BACKUP IN A NETWORKED COMPUTING ENVIRONMENT - Embodiments of the present invention provide a hybrid (e.g., local and remote) approach for data backup in a networked computing environment (e.g., a cloud computing environment). In a typical embodiment, a set of storage configuration parameters corresponding to a set of data to be backed up is received and stored in a computer data structure. The set of storage configuration parameters can comprise at least one of the following: a recovery time objective (RTO), a recovery point objective (RPO), and a desired type of protection for the set of data. Regardless, the set of data is compared to previously stored data to identify at least one of the following: portions of the set of data that have commonality with the previously stored data; and portions of the set of data that are unique to the set of data (i.e., not in common with any of the previously stored data). The above-described process is referred to herein as “de-duplication”. A storage solution is then determined based on the set of storage configuration parameters. In general, the storage solution identifies at least one local storage resource and at least one remote storage resource (e.g., a cloud storage resource) for backing up the portions of the set of data that are unique to the set of data. Once the storage solution has been determined, the unique portions of the set of data will be stored in accordance therewith. | 01-03-2013 |
20130110793 | DATA DE-DUPLICATION IN COMPUTER STORAGE SYSTEMS | 05-02-2013 |
20130261826 | OPTIMIZING POWER CONSUMPTION BY DYNAMIC WORKLOAD ADJUSTMENT - A method and system for optimizing power consumption of a data center by dynamic workload adjustment. At least one candidate workload solution for the data center is generated. Each candidate workload solution represents a respective application map that specifies a respective workload distribution among application programs of the data center. Workload of the data center is dynamically adjusted from a current workload distribution to an optimal workload solution. The optimal workload solution is a candidate workload solution of the at least one candidate workload solution having a lowest sum of a respective power cost and a respective migration cost. Dynamically adjusting the workload of the data center includes: estimating a respective overall cost of each candidate workload solution, selecting the optimal workload solution that has a lowest overall cost as determined from the estimating, and transferring the optimal workload solution to devices of a computer system for deployment. | 10-03-2013 |
20130290258 | TRANSITIONING APPLICATION REPLICATION CONFIGURATIONS IN A NETWORKED COMPUTING ENVIRONMENT - Embodiments of the present invention provide an approach for providing non-disruptive transitioning of application replication configurations and proactive analysis of possible error scenarios. Specifically, under embodiments of the present invention, a common integration model (CIM)-compatible representation of a system replication plan is provided in a computer data structure. Based on the representation, a hierarchical tree data structure having a set of nodes is created. A set of system configuration updates pertaining to the set of nodes are then classified (e.g., based upon the type of configuration update). Once the set of nodes has been classified, the set of nodes may then be analyzed to determine if any nodes of the set are isomorphic. If so, the plan can be modified accordingly. In any event, the replication plan (or modified replication plan) may then be implemented. | 10-31-2013 |
20130298131 | CONTINUOUS OPTIMIZATION OF ARCHIVE MANAGEMENT SCHEDULING BY USE OF INTEGRATED CONTENT-RESOURCE ANALYTIC MODEL - A method and associated system for continuously optimizing data archive management scheduling. A flow network is modeled. The flow network represents data content, software programs, physical devices, and communication capacity of the archive management system in various levels of vertices such that an optimal path in the flow network from a task of at least one archive management task to a worker program of the archive management system represents an optimal initial schedule for the worker program to perform the task. | 11-07-2013 |
20140074794 | OPTIMIZING RESTORATION OF DEDUPLICATED DATA - A computer identifies a plurality of data retrieval requests that may be serviced using a plurality of unique data chunks. The computer services the data retrieval requests by utilizing at least one of the unique data chunks. At least one of the unique data chunks can be utilized for servicing two or more of the data retrieval requests. The computer determines a servicing sequence for the plurality of data retrieval requests such that the two or more of the data retrieval requests that can be serviced utilizing the at least one of the unique data chunks are serviced consecutively. The computer services the plurality of data retrieval requests according to the servicing sequence. | 03-13-2014 |
20140223122 | MANAGING VIRTUAL MACHINE PLACEMENT IN A VIRTUALIZED COMPUTING ENVIRONMENT - A method for determining that first and second virtual machines, that currently execute in first and second host computing systems, respectively, should both execute within a same host computing system. The method includes determining that the first and second virtual machines have accessed same data more often than a third and fourth virtual machines have accessed said same data. Based in part on this determination, the method includes determining that the first and second virtual machines should execute in a same host computing system having a same cache memory for both the first and second virtual machines and that the third and fourth virtual machines should execute on one or more different host computing systems than said same host computing system. | 08-07-2014 |
20140244590 | HYBRID DATA BACKUP IN A NETWORKED COMPUTING ENVIRONMENT - Embodiments of the present invention provide a hybrid (e.g., local and remote) approach for data backup in a networked computing environment (e.g., a cloud computing environment). In a typical embodiment, a set of storage configuration parameters corresponding to a set of data to be backed up is received and stored in a computer data structure. The set of storage configuration parameters can comprise at least one of the following: a recovery time objective (RTO), a recovery point objective (RPO), and a desired type of protection for the set of data. Regardless, the set of data is compared to previously stored data to identify at least one of the following: portions of the set of data that have commonality with the previously stored data; and portions of the set of data that are unique to the set of data (i.e., not in common with any of the previously stored data). The above-described process is referred to herein as “de-duplication”. A storage solution is then determined based on the set of storage configuration parameters. In general, the storage solution identifies at least one local storage resource and at least one remote storage resource (e.g., a cloud storage resource) for backing up the portions of the set of data that are unique to the set of data. Once the storage solution has been determined, the unique portions of the set of data will be stored in accordance therewith. | 08-28-2014 |
20140330795 | OPTIMIZING RESTORATION OF DEDUPLICATED DATA - A computer identifies a plurality of data retrieval requests that may be serviced using a plurality of unique data chunks. The computer services the data retrieval requests by utilizing at least one of the unique data chunks. At least one of the unique data chunks is utilized for servicing two or more of the data retrieval requests. The computer determines a servicing sequence for the plurality of data retrieval requests such that the two or more of the data retrieval requests that are serviced utilizing the at least one of the unique data chunks are serviced consecutively. The computer services the plurality of data retrieval requests according to the servicing sequence. | 11-06-2014 |
20150339160 | CONTINUOUS OPTIMIZATION OF ARCHIVE MANAGEMENT SCHEDULING BY USE OF INTEGRATED CONTENT-RESOURCE ANALYTIC MODEL - A method and associated system for continuously optimizing data archive management scheduling. A flow network is modeled, which creates vertexes organized in multiple levels and creating multiple edges sequentially connecting the vertexes of the multiple levels. The multiple levels consist of N+1 levels denoted as LEVEL | 11-26-2015 |
20160062651 | CACHE MANAGEMENT FOR SEQUENTIAL WRITE STORAGE - Embodiments of the invention relate to cache management of sequential write storage. Cache states of cache blocks in cache storage are tracked. The tracking incudes creating a migration candidate list that organizes the cache blocks into virtual volumes. Based on determining that a cache migration threshold has been reached, at least a subset of the cache blocks are selected from the migration candidate list for migration. The selected cache blocks are ordered into a sequential order based on the migration candidate list. At least a subset of the selected cache blocks are migrated in the sequential order, the migrating including writing contents of the selected cache blocks to the sequential write storage. | 03-03-2016 |
20160077972 | Efficient and Consistent Para-Virtual I/O System - Embodiments of the invention relate to a para-virtual I/O system. A consistent para-virtual I.O system architecture is provided with a new virtual disk interface and a semantic journaling mechanism. The virtual disk interface is extended with two primitives for flushing and ordering I/O, both of the primitives being exported to para-virtual I/O drivers in a guest operating system. The ordering primitive guarantees ordering of preceeding writes, and the flushing primitive enforces order and durability. The guest drivers selectively uses both of these primitives based on semantics of the data being persisted from the para-virtual cache hierarchy to physical disk. The order of committed writes is enforced in order to enable a consistent start recovered after a crash. | 03-17-2016 |
20160117133 | PARITY LOGS FOR RAID SYSTEMS WITH VARIABLE CAPACITY MEDIA - Embodiments of the invention provide parity logs for raid systems with variable-capacity media. In one embodiment, a system includes a first set of data storage media devices having variable capacity. The storage devices include a data portion of a parity data set for storing write data being striped to the first. The system further includes a second set of data storage media devices having variable capacity. The second set includes a linear address space of blocks for storing a parity portion of the parity data set. The linear address space is written in a log form. The first and second sets comprise at least one array in a RAID configuration. The system writes the parity portion of the parity data set to the second set, which enables each storage device among the first set to be written to full capacity. | 04-28-2016 |
20160117222 | TIME MULTIPLEXED REDUNDANT ARRAY OF INDEPENDENT TAPES - Embodiments relate to a computer system for storing data on a time multiplexed redundant array of independent tapes. An aspect includes a memory device that buffers data received by the computer system to be written to a set of tape data storage devices. The data is written to the set of tape data storage devices in blocks that form parity stripes across the set of tape data storage device. Aspects further includes a tape drive that writes data to one of the set of tape data storage devices at a time in a tape-sequential manner and a processor that computes a parity value for each of the parity stripes. The tape drive writes the parity values for each of the parity stripes to a last subset of tapes of the set of tape data storage devices. | 04-28-2016 |
20160140133 | METHOD AND APPARATUS FOR THE GENERATION, ORGANIZATION, STORAGE AND RETRIEVAL OF TIME STAMPED BLOCKS OF DATA - Embodiments disclosed herein provide systems, methods, and computer readable media to enhance the organization, storage, and retrieval of data. In a particular embodiment, a method provides storing a plurality of incremental data versions in a data repository and maintaining first time information for data items in each of the incremental data versions. The method further provides identifying a first data version of the plurality of incremental data versions and writing data in the data repository to create a second data version based the first data version. The method then provides second time information associated with the creation of the second data and creation of the first data version. | 05-19-2016 |
20160140191 | METHOD AND APPARATUS FOR THE STORAGE AND RETRIEVAL OF TIME STAMPED BLOCKS OF DATA - Embodiments disclosed herein provide systems, methods, and computer readable storage media for time-based storage and retrieval of data items. In a particular embodiment, a method provides receiving a point-in-time data request. Using metadata associated with data items stored in a secondary data repository, the method provides determining a mapping between the point-in-time data request and one or more of the data items. The method further includes providing the one or more data items in response to the point-in-time data request. | 05-19-2016 |
Patent application number | Description | Published |
20110253670 | METHODS FOR ETCHING SILICON-BASED ANTIREFLECTIVE LAYERS - Methods for etching silicon-based antireflective layers are provided herein. In some embodiments, a method of etching a silicon-based antireflective layer may include providing to a process chamber a substrate having a multiple-layer resist thereon, the multiple-layer resist comprising a patterned photoresist layer defining features to be etched into the substrate disposed above a silicon-based antireflective coating; and etching the silicon-based antireflective layer through the patterned photoresist layer using a plasma formed from a process gas having a primary reactive agent comprising a chlorine-containing gas. In some embodiments, the chlorine-containing gas is chlorine (Cl | 10-20-2011 |
20140017898 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a plasma process. The method also involves, in the same operation, removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer. | 01-16-2014 |
20140120726 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer. | 05-01-2014 |
20140199851 | METHOD OF PATTERNING A SILICON NITRIDE DIELECTRIC FILM - Methods of patterning silicon nitride dielectric films are described. For example, a method of isotropically etching a dielectric film involves partially modifying exposed regions of a silicon nitride layer with an oxygen-based plasma process to provide a modified portion and an unmodified portion of the silicon nitride layer. The method also involves removing, selective to the unmodified portion, the modified portion of the silicon nitride layer with a second plasma process. | 07-17-2014 |
20150118832 | METHODS FOR PATTERNING A HARDMASK LAYER FOR AN ION IMPLANTATION PROCESS - Embodiments of the present invention provide a methods for patterning a hardmask layer with good process control for an ion implantation process, particularly suitable for manufacturing the fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of patterning a hardmask layer disposed on a substrate includes forming a planarization layer over a hardmask layer disposed on a substrate, disposing a patterned photoresist layer over the planarization layer, patterning the planarization layer and the hardmask layer uncovered by the patterned photoresist layer in a processing chamber, exposing a first portion of the underlying substrate, and removing the planarization layer from the substrate. | 04-30-2015 |
20150262834 | TEMPERATURE RAMPING USING GAS DISTRIBUTION PLATE HEAT - A method for etching a dielectric layer disposed on a substrate is provided. The method includes de-chucking the substrate from an electrostatic chuck in an etching processing chamber, and cyclically etching the dielectric layer while the substrate is de-chucked from the electrostatic chuck. The cyclical etching includes remotely generating a plasma in an etching gas mixture supplied into the etching processing chamber to etch the dielectric layer disposed on the substrate at a first temperature. Etching the dielectric layer generates etch byproducts. The cyclical etching also includes vertically moving the substrate towards a gas distribution plate in the etching processing chamber, and flowing a sublimation gas from the gas distribution plate towards the substrate to sublimate the etch byproducts. The sublimation is performed at a second temperature, wherein the second temperature is greater than the first temperature. | 09-17-2015 |
20150380215 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer. | 12-31-2015 |
Patent application number | Description | Published |
20080230518 | GAS FLOW DIFFUSER - A method and apparatus for providing flow into a processing chamber are provided. In one embodiment, a vacuum processing chamber is provided that includes a chamber body having an interior volume, a substrate support disposed in the interior volume and a gas distribution assembly having an asymmetrical distribution of gas injection ports. In another embodiment, a method for vacuum processing a substrate is provided that includes disposing a substrate on a substrate support within in a processing chamber, flowing process gas into laterally into a space defined above a gas distribution plate positioned in the processing chamber over the substrate, and processing the substrate in the presence of the processing gas. | 09-25-2008 |
20090159566 | METHOD AND APPARATUS FOR CONTROLLING TEMPERATURE OF A SUBSTRATE - A pedestal assembly and method for controlling temperature of a substrate during processing is provided. In one embodiment, method for controlling a substrate temperature during processing includes placing a substrate on a substrate pedestal assembly in a vacuum processing chamber, controlling a temperature of the substrate pedestal assembly by flowing a heat transfer fluid through a radial flowpath within the substrate pedestal assembly, the radial flowpath including both radially inward and radially outward portions, and plasma processing the substrate on the temperature controlled substrate pedestal assembly. In another embodiment, plasma processing may be at least one of a plasma treatment, a chemical vapor deposition process, a physical vapor deposition process, an ion implantation process or an etch process, among others. | 06-25-2009 |
20100099266 | ETCH REACTOR SUITABLE FOR ETCHING HIGH ASPECT RATIO FEATURES - Embodiments of the invention provide a method and apparatus that enables plasma etching of high aspect ratio features. In one embodiment, a method for etching is provided that includes providing a substrate having a patterned mask disposed on a silicon layer in an etch reactor, providing a gas mixture of the reactor, maintaining a plasma formed from the gas mixture, wherein bias power and RF power provided the reactor are pulsed, and etching the silicon layer in the presence of the plasma. | 04-22-2010 |
20110180243 | APPARATUS FOR CONTROLLING TEMPERATURE UNIFORMITY OF A SUBSTRATE - Apparatus for controlling thermal uniformity of a substrate is provided herein. In some embodiments, the thermal uniformity of the substrate may be controlled to be more uniform. In some embodiments, the thermal uniformity of the substrate may be controlled to be non-uniform in a desired pattern. In some embodiments, an apparatus for controlling thermal uniformity of a substrate may include a substrate support having a support surface to support a substrate thereon; and a plurality of flow paths having a substantially equivalent fluid conductance disposed within the substrate support to flow a heat transfer fluid beneath the support surface. | 07-28-2011 |
20120091104 | MULTI-ZONED PLASMA PROCESSING ELECTROSTATIC CHUCK WITH IMPROVED TEMPERATURE UNIFORMITY - An electrostatic chuck assembly including a dielectric layer with a top surface to support a workpiece. A cooling channel base disposed below the dielectric layer includes a plurality of inner fluid conduits disposed beneath an inner portion of the top surface, and a plurality of outer fluid conduits disposed beneath an outer portion of the top surface. A chuck assembly includes a thermal break disposed within the cooling channel base between the inner and outer fluid conduits. A chuck assembly includes a fluid distribution plate disposed below the cooling channel base and the base plate to distribute a heat transfer fluid delivered from a common input to each inner or outer fluid conduit. The branches of the inner input manifold may have substantially equal fluid conductance. | 04-19-2012 |
20120091108 | METHODS AND APPARATUS FOR CONTROLLING SUBSTRATE TEMPERATURE IN A PROCESS CHAMBER - Methods and apparatus for controlling the temperature of a substrate during processing are provided herein. In some embodiments, an apparatus for retaining and controlling substrate temperature may include a puck of dielectric material; an electrode disposed in the puck proximate a surface of the puck upon which a substrate is to be retained; and a plurality of heater elements disposed in the puck and arranged in concentric rings to provide independent temperature control zones. | 04-19-2012 |
20120097332 | SUBSTRATE SUPPORT WITH SYMMETRICAL FEED STRUCTURE - Apparatus for processing a substrate is disclosed herein. In some embodiments, a substrate support may include a substrate support having a support surface for supporting a substrate the substrate support having a central axis; a first electrode disposed within the substrate support to provide RF power to a substrate when disposed on the support surface; an inner conductor coupled to the first electrode about a center of a surface of the first electrode opposing the support surface, wherein the inner conductor is tubular and extends from the first electrode parallel to and about the central axis in a direction away from the support surface of the substrate support; an outer conductor disposed about the inner conductor; and an outer dielectric layer disposed between the inner and outer conductors, the outer dielectric layer electrically isolating the outer conductor from the inner conductor. The outer conductor may be coupled to electrical ground. | 04-26-2012 |
20120132397 | TEMPERATURE CONTROL IN PLASMA PROCESSING APPARATUS USING PULSED HEAT TRANSFER FLUID FLOW - Methods and systems for controlling temperatures in plasma processing chamber via pulsed application of heating power and pulsed application of cooling power. In an embodiment, temperature control is based at least in part on a feedforward control signal derived from a plasma power input into the processing chamber. In further embodiments, fluid levels in each of a hot and cold reservoir coupled to the temperature controlled component are maintained in part by a passive leveling pipe coupling the two reservoirs. In another embodiment, digital heat transfer fluid flow control valves are opened with pulse widths dependent on a heating/cooling duty cycle value and a proportioning cycle having a duration that has been found to provide good temperature control performance. | 05-31-2012 |
20140020834 | APPARATUS FOR ETCHING HIGH ASPECT RATIO FEATURES - Embodiments of the invention provide a method and apparatus, such as a processing chamber, suitable for etching high aspect ratio features. Other embodiments include a showerhead assembly for use in the processing chamber. In one embodiment, a processing chamber includes a chamber body having a showerhead assembly and substrate support disposed therein. The showerhead assembly includes at least two fluidly isolated plenums, a region transmissive to an optical metrology signal, and a plurality of gas passages formed through the showerhead assembly fluidly coupling the plenums to the interior volume of the chamber body. | 01-23-2014 |
20140346743 | MULTI-ZONED PLASMA PROCESSING ELECTROSTATIC CHUCK WITH IMPROVED TEMPERATURE UNIFORMITY - An electrostatic chuck assembly including a dielectric layer with a top surface to support a workpiece. A cooling channel base disposed below the dielectric layer includes a plurality of inner fluid conduits disposed beneath an inner portion of the top surface, and a plurality of outer fluid conduits disposed beneath an outer portion of the top surface. A chuck assembly includes a thermal break disposed within the cooling channel base between the inner and outer fluid conduits. A chuck assembly includes a fluid distribution plate disposed below the cooling channel base and the base plate to distribute a heat transfer fluid delivered from a common input to each inner or outer fluid conduit. The branches of the inner input manifold may have substantially equal fluid conductance. | 11-27-2014 |
20150316941 | TEMPERATURE CONTROL IN PLASMA PROCESSING APPARATUS USING PULSED HEAT TRANSFER FLUID FLOW - Methods and systems for controlling temperatures in plasma processing chamber via pulsed application of heating power and pulsed application of cooling power. In an embodiment, temperature control is based at least in part on a feedforward control signal derived from a plasma power input into the processing chamber. In further embodiments, fluid levels in each of a hot and cold reservoir coupled to the temperature controlled component are maintained in part by a passive leveling pipe coupling the two reservoirs. In another embodiment, digital heat transfer fluid flow control valves are opened with pulse widths dependent on a heating/cooling duty cycle value and a proportioning cycle having a duration that has been found to provide good temperature control performance. | 11-05-2015 |
20150371877 | SUBSTRATE SUPPORT WITH SYMMETRICAL FEED STRUCTURE - Apparatus for processing a substrate is disclosed herein. In some embodiments, a substrate support may include a substrate support having a support surface for supporting a substrate the substrate support having a central axis; a first electrode disposed within the substrate support to provide RF power to a substrate when disposed on the support surface; an inner conductor coupled to the first electrode about a center of a surface of the first electrode opposing the support surface, wherein the inner conductor is tubular and extends from the first electrode parallel to and about the central axis in a direction away from the support surface of the substrate support; an outer conductor disposed about the inner conductor; and an outer dielectric layer disposed between the inner and outer conductors, the outer dielectric layer electrically isolating the outer conductor from the inner conductor. The outer conductor may be coupled to electrical ground. | 12-24-2015 |
Patent application number | Description | Published |
20140237601 | OPERATION OF A DUAL INSTRUCTION PIPE VIRUS CO-PROCESSOR - Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a content object is stored by a general purpose processor to a system memory. The memory has stored therein a page directory containing information for translating virtual addresses to physical addresses. Multiple most recently used entries of the page directory are cached, by a virus co-processor, within translation lookaside buffers (TLBs) implemented within an on-chip cache of the co-processor. Instructions are read by the co-processor, from a virus signature memory of the co-processor. The instructions contain op-codes of a first and second instruction type. Instructions of the first type are assigned to a first instruction pipe of the co-processor. An instruction assigned to the first instruction pipe is executed including accessing the content object by performing direct virtual memory addressing of the system memory and comparing the content object against a string. | 08-21-2014 |
20140380483 | OPERATION OF A DUAL INSTRUCTION PIPE VIRUS CO-PROCESSOR - Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a content object that is to be virus processed is stored by a general purpose processor to a system memory. Virus scan parameters for the content object are set up by the general purpose processor. Instructions from a virus signature memory of a virus co-processor are read by the virus co-processor based on the virus scan parameters. The instructions contain op-codes of a first instruction type and op-codes of a second instruction type. Those of the instructions containing op-codes of the first instruction type are assigned to a first instruction pipe of multiple instruction pipes of the virus co-processor for execution. An instruction of the assigned instructions containing op-codes of the first instruction type is executed by the first instruction pipe including accessing a portion of the content object from the system memory. | 12-25-2014 |
20150055481 | CONTEXT-AWARE PATTERN MATCHING ACCELERATOR - Methods and systems for improving accuracy, speed, and efficiency of context-aware pattern matching are provided. According to one embodiment, a packet stream is received and pre-matched by an acceleration device with one or more conditions to identify packets meeting the one or more conditions. The acceleration device then correlates at least one identified packet based on the one or more conditions to generate matching tokens of the packet that meet the one or more conditions and sends, to one or more processors of the acceleration device, the matching tokens along with identifiers of the one or more conditions so that the processors can process the matching tokens and the identifiers of the one or more conditions based on one or more of context aware string matching, regular expression matching, and packet field value matching to extract packets that match context of the one or more conditions. | 02-26-2015 |
20150101054 | OPERATION OF A DUAL INSTRUCTION PIPE VIRUS CO-PROCESSOR - Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a system includes a system memory, a general purpose processor, an instruction memory and a virus co-processor. The processor is coupled to the system memory and operable to store a data segment therein. The instruction memory includes a virus signature, having a first instruction of a first instruction type and a second instruction of a second instruction type, for detection of a computer virus. The co-processor is coupled to the instruction memory and the system memory and is operable to access the data segment. The co-processor includes first and second instruction pipes operable to execute the first and second instruction types, respectively. The first and second instruction pipes include first and second write back circuits, respectively, that are linked to ensure a ordered write back of instructions. | 04-09-2015 |
20150277763 | VIRTUALIZATION IN A MULTI-HOST ENVIRONMENT - Methods and systems for implementing improved partitioning and virtualization in a multi-host environment are provided. According to one embodiment, multiple devices, including CPUs and peripherals, coupled with a system via an interconnect matrix/bus are associated with a shared memory logically partitioned into multiple domains. A first domain is associated with a first set of the devices and a second domain is associated with a second set of the devices. A single shared virtual map module (VMM), maps a memory access request to an appropriate partitioned domain of the memory to which the originating device has been assigned based on an identifier associated with the device and further based on they type of memory access. The VMM causes a memory controller to perform memory access on behalf of the device by outputting a physical address based on the identified domain and the virtual address specified by the request. | 10-01-2015 |
20150326534 | CONTEXT-AWARE PATTERN MATCHING ACCELERATOR - Methods and systems for improving accuracy, speed, and efficiency of context-aware pattern matching are provided. According to one embodiment, a packet stream is received by a first stage of a CPMP hardware accelerator of a network device. A pre-matching process is performed by the first stage to identify a candidate packet that matches a string or over-flow pattern associated with IPS or ADC rules. A candidate rule is identified based on a correlation of results of the pre-matching process. The candidate packet is tokened to produce matching tokens and corresponding locations. A full-match process is performed on the candidate packet by a second stage of the CPMP hardware accelerator to determine whether it satisfies the candidate rule by performing one or more of (i) context-aware pattern matching, (ii) context-aware string matching and (iii) regular expression matching based on contextual information, the matching tokens and the corresponding locations. | 11-12-2015 |
20150331815 | NETWORK INTERFACE CARD RATE LIMITING - Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network appliance through a bus system. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are transmitted from the NIC to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing transmission of the received data packets from the NIC to the host CPU for processing. | 11-19-2015 |
20150332046 | OPERATION OF A DUAL INSTRUCTION PIPE VIRUS CO-PROCESSOR - Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a content object that is to be virus processed is stored by a general purpose processor to a system memory. Virus scan parameters for the content object are set up by the general purpose processor. Instructions from a virus signature memory of a virus co-processor are read by the virus co-processor based on the virus scan parameters. The instructions contain op-codes of a first instruction type and op-codes of a second instruction type. Those of the instructions containing op-codes of the first instruction type are assigned to a first instruction pipe of multiple instruction pipes of the virus co-processor for execution. An instruction of the assigned instructions containing op-codes of the first instruction type is executed by the first instruction pipe including accessing a portion of the content object from the system memory. | 11-19-2015 |
20160094519 | DIRECT CACHE ACCESS FOR NETWORK INPUT/OUTPUT DEVICES - Methods and systems for improving efficiency of direct cache access (DCA) are provided. According to one embodiment, a set of DCA control settings are defined by a network I/O device of a network security device for each of multiple I/O device queues based on network security functionality performed by corresponding CPUs of a host processor. The control settings specify portions of network packets that are to be copied to a cache of the corresponding CPU. A packet is received by the network I/O device. Information associated with the packet is queued onto an I/O device queue. The information is then transferred from the I/O device queue to a host memory of the network security device. Based on the control settings for the I/O device queue only those portions of the information corresponding to the one or more specified portions are copied to the cache of the corresponding CPU. | 03-31-2016 |
Patent application number | Description | Published |
20100073827 | TMR device with novel free layer structure - A TMR sensor that includes a free layer having at least one B-containing (BC) layer made of CoFeB, CoFeBM, CoB, COBM, or CoBLM, and a plurality of non-B containing (NBC) layers made of CoFe, CoFeM, or CoFeLM is disclosed where L and M are one of Ni, Ta, Ti, W, Zr, Hf, Tb, or Nb. One embodiment is represented by (NBC/BC) | 03-25-2010 |
20100123208 | MR device with synthetic free layer structure - A magneto-resistive device having a large output signal as well as a high signal-to-noise ratio is described along with a process for forming it. This improved performance was accomplished by expanding the free layer into a multilayer laminate comprising at least three ferromagnetic layers separated from one another by antiparallel coupling layers. The ferromagnetic layer closest to the transition layer must include CoFeB while the furthermost layer is required to have low Hc as well as a low and negative lambda value. One possibility for the central ferromagnetic layer is NiFe but this is not mandatory. | 05-20-2010 |
20140138783 | MR Device with Synthetic Free Layer Structure - A magneto-resistive device having a large output signal as well as a high signal-to-noise ratio is described along with a process for forming it. This improved performance was accomplished by expanding the free layer into a multilayer laminate comprising at least three ferromagnetic layers separated from one another by antiparallel coupling layers. The ferromagnetic layer closest to the transition layer must include CoFeB while the furthermost layer is required to have low Hc as well as a low and negative lambda value. One possibility for the central ferromagnetic layer is NiFe but this is not mandatory. | 05-22-2014 |
20150248902 | TMR Device with Novel Free Layer Structure - A TMR sensor that includes a free layer having at least one B-containing (BC) layer made of CoFeB, CoFeBM, CoB, CoBM, or CoBLM, and a plurality of non-B containing (NBC) layers made of CoFe, CoFeM, or CoFeLM is disclosed where L and M are one of Ni, Ta, Ti, W, Zr, Hf, Tb, or Nb. One embodiment is represented by (NBC/BC) | 09-03-2015 |
20150249210 | TMR Device with Novel Free Layer Structure - A method of fabricating a TMR sensor that includes a free layer having at least one B-containing (BC) layer made of CoFeB, CoFeBM, CoB, CoBM, or CoBLM, and a plurality of non-B containing (NBC) layers made of CoFe, CoFeM, or CoFeLM is disclosed where L and M are one of Ni, Ta, Ti, W, Zr, Hf, Tb, or Nb. In every embodiment, a NBC layer contacts the tunnel barrier and NBC layers each with a thickness from 2 to 8 Angstroms are formed in alternating fashion with one or more BC layers each 10 to 80 Angstroms thick. Total free layer thickness is <100 Angstroms. The TMR sensor may be annealed with a one step or two step process. The free layer configuration described herein enables a significant noise reduction (SNR enhancement) while realizing a high TMR ratio, low magnetostriction, low RA, and low Hc values. | 09-03-2015 |