Patent application number | Description | Published |
20130287389 | FIBER CHANNEL 1:N REDUNDANCY - Network devices, systems, and methods, including executable instructions and/or logic thereon to achieve fiber channel one for N (1:N) redundancy. A network device includes a processing resource coupled to a memory. The memory includes program instructions executed by the processing resource to group a number of switches in a 1:N cluster and provide each switch with a (virtual) A_Port link to all members of the 1:N cluster. If a failure of a fiber channel over ethernet forwarder (FCF) occurs, the program instructions execute to re-establish or redirect a connection over an alternate path through a redundant FCF without having to synchronize a connection state across all switches in the cluster. | 10-31-2013 |
20140029608 | FIBRE CHANNEL HOST VIRTUALIZATION - A method for fibre channel (FC) host virtualization includes determining a virtual N_Port identification (ID) that is assigned and used by a host to route a frame from the host to a switch of a FC storage area network (SAN) fabric, and determining a FC SAN fabric based location N_Port ID that is assigned by the FC SAN fabric to the host to route the frame within the FC SAN fabric. The method further includes mapping, by a processor, the host assigned virtual N_Port ID to the FC SAN fabric based location N_Port ID. | 01-30-2014 |
20140029609 | UPDATING TABLE DATA IN NETWORK DEVICE - One example includes a network device. The network device includes a processor and a memory communicatively coupled to the processor. The memory stores instructions causing the processor, after execution of the instructions by the processor, to receive a plurality of frames including table data, each frame including a sequence number, and update a table in the memory based on the table data and the sequence number of each received frame. | 01-30-2014 |
20140280885 | FLOW CONTROL TRANSMISSION - An example of flow control transmission can comprise receiving a transmission instruction at a transmitter. Data can be sent from the transmitter at a rate of transmission based on the transmission instruction. A rate of transmission can be monitored over a time interval to determine a difference between a minimum rate of transmission and the monitored rate of transmission over the time interval. The transmission instruction can be overridden and data released to maintain the minimum rate of transmission based on the monitored difference. | 09-18-2014 |
20150043584 | Converged Fabric for FCoE - Network devices, systems, and methods, including program instructions are disclosed which provide a converged fabric for Fiber Channel over Ethernet (FCoE). A network device includes a Fiber Channel Controller (FCC), located outside of a lossless Ethernet network. The FCC has a processing resource coupled to a memory. The memory includes program instructions executed by the processing resource to terminate Fiber Channel (FC) Initialization Protocol (FIP) frames, generated to and by initiator and target devices, on the FCC. | 02-12-2015 |
Patent application number | Description | Published |
20090055697 | ERROR SCANNING IN FLASH MEMORY - Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed. | 02-26-2009 |
20090259807 | FLASH MEMORY ARCHITECTURE WITH SEPARATE STORAGE OF OVERHEAD AND USER DATA - A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data. Current overhead segments of a dedicated overhead block can be consolidated and moved to a new dedicated overhead block. | 10-15-2009 |
20090274017 | MIXED-SIGNAL SINGLE-CHIP INTEGRATED SYSTEM ELECTRONICS FOR DATA STORAGE DEVICES - An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices. | 11-05-2009 |
20100313077 | ERROR SCANNING IN FLASH MEMORY - Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed. | 12-09-2010 |
20120110399 | ERROR SCANNING IN FLASH MEMORY - Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed. | 05-03-2012 |
20120185754 | FLASH MEMORY ARCHITECTURE WITH SEPARATE STORAGE OF OVERHEAD AND USER DATA - A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data that comprises ECC data that is used for error checking with respect to the user data in the dedicated data blocks. The dedicated data blocks can be erased without erasing the ECC data that is used for error checking with respect to the user data in the dedicated data blocks. | 07-19-2012 |
20130132805 | ERROR SCANNING IN FLASH MEMORY - Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed. | 05-23-2013 |