Patent application number | Description | Published |
20090053857 | SEMICONDUCTOR PACKAGING METHOD - The present invention relates to a semiconductor packaging method. The method comprises (S | 02-26-2009 |
20090278577 | SEMICONDUCTOR DEVICE INCLUDING PHASE DETECTOR - A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal. | 11-12-2009 |
20100007375 | TERMINATION RESISTANCE CIRCUIT - A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal. | 01-14-2010 |
20100013535 | LATCH CIRCUIT - A latch circuit includes a data input/output unit configured to form a current path through a first node in response to an input data to output an output data, a holding unit configured to form a current path through a second node in response to the output data to store the output data, and a clock input unit coupled to the first and second nodes in parallel in response to a clock. | 01-21-2010 |
20100061157 | DATA OUTPUT CIRCUIT - A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data. | 03-11-2010 |
20100109923 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of synchronization blocks configured to sequentially synchronize a plurality of input signals swinging in a complementary metal oxide semiconductor (CMOS) region with multi-phase clock signals to output a plurality of output signals swinging in a current mode logic (CML) region, a plurality of first swing region converting blocks configured to convert the plurality of output signals to a plurality of converted output signals swinging in the CMOS region, a serialization block configured to serialize a plurality of converted output signals, thereby outputting a serialized signal swinging in the CML region, and a second swing region converting block configured to convert the serialized signal to a serialized output signal swinging in the CMOS region. | 05-06-2010 |
20100157643 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes non-inversion repeaters that non-invert data and output the inverted data; and inversion repeaters that invert data and output the inverted data. The non-inversion repeaters or the inversion repeaters are arranged on a first data line and a second data line at a predetermined distance, respectively, which are parallel with each other and the most adjacent to each other and the non-inversion repeater or the inversion repeater is arranged at first positions corresponding to the first data line and the second data line, respectively. The non-inversion repeaters are arranged on one of the first data line and the second data line while the inversion repeaters are arranged on the other first data line and the second data line, at second positions except for the first arrangement positions of positions corresponding to the first data line and the second data line, respectively. | 06-24-2010 |
20110121860 | SEMICONDUCTOR DEVICE - A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second voltage level lower than the first voltage level, and a CML clock transfer buffering unit configured to use a second power supply voltage as a power supply voltage and buffer the CML clock, which is transferred from the swing level shifting unit and swings around the second voltage level. | 05-26-2011 |
20110140768 | INTERNAL VOLTAGE GENERATOR - An internal voltage generator includes: a detection unit configured to detect a level of an internal voltage in comparison to a reference voltage; a first driving unit configured to discharge an internal voltage terminal, through which the internal voltage is outputted, in response to an output signal of the detection unit; a current detection unit configured to detect a discharge current flowing through the first driving unit; and a second driving unit configured to charge the internal voltage terminal in response to an output signal of the current detection unit. | 06-16-2011 |
20110291759 | RAIL-TO-RAIL AMPLIFIER - A rail-to-rail amplifier includes an NMOS type amplification unit configured to perform an amplification operation on differential input signals in a domain in which DC levels of the differential input signals are higher than a first threshold value, a PMOS type folded-cascode amplification unit configured to perform an amplification operation on the differential input signals in a domain in which the DC levels of the differential input signals are lower than a second threshold value which is higher than the first threshold value, the PMOS type folded-cascode amplification unit being cascade-coupled to the NMOS type amplification unit, and an adaptive biasing unit configured to interrupt a current path of the PMOS type folded-cascode amplification unit in a domain in which the DC levels of the differential input signals are higher than the second threshold value in response to the differential input signals. | 12-01-2011 |
20130176521 | PHOTO ALIGNMENT METHOD, EXPOSURE SYSTEM FOR PERFORMING THE SAME AND LIQUID CRYSTAL DISPLAY PANEL MANUFACTURED BY THE SAME - In a photo alignment method, a substrate and a mask are aligned so that the substrate is spaced apart from the mask by a predetermined gap. An organic layer is formed on the substrate. The mask has a transmission portion and a light blocking portion. Light is irradiated through the mask in a direction substantially parallel with an interface between the transmission portion and the light blocking portion of the mask. Polymer chains are formed on an upper portion of the organic layer. The polymer chains are aligned in an alignment direction toward an incident direction of the light. Locations of the substrate and the mask are sensed in real time. The mask is transported to a predetermined location with respect to the substrate based on the sensed locations of the substrate and the mask. | 07-11-2013 |
20130227198 | FLASH MEMORY DEVICE AND ELECTRONIC DEVICE EMPLOYING THEREOF - A flash memory device and an electronic device employing thereof are provided for efficiently processing data that is larger than a page size of a data block and for processing data that is smaller than the page size of the data block. The flash memory device preferably includes a plurality of flash arrays therein and the plurality of flash arrays is divided into partitions depending on at least two or more page sizes, thereby advantageously improving the performance of random write. | 08-29-2013 |
20130242245 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A display panel includes a gate line, a data line, a pixel electrode formed adjacent to the gate and data lines on a lower substrate and a first alignment film disposed in a first domain disposed on the pixel electrode and in a second domain formed on pixel electrode. The first domain is aligned in a first direction and the second domain is aligned in a second direction which is different from the first direction. The upper substrate opposes the lower substrate and includes a common electrode disposed on the upper substrate and a second alignment film disposed on the common electrode at a third domain corresponding to the first domain and at a fourth domain corresponding to the second domain. The liquid crystal layer is disposed between the lower substrate and the upper substrate and includes liquid crystals defined by a plurality of pixel areas. | 09-19-2013 |
20130308390 | METHOD AND APPARATUS FOR PROGRAMMING DATA IN NON-VOLATILE MEMORY DEVICE - A method and an apparatus for programming data, and a method and an apparatus for setting a data programming mode used for the same are provided. The method for programming data in a non-volatile memory device includes determining a programming mode to be used for data programming among at least two programming modes prescribing different verify voltages for cells to be programmed, based on set mode information, and programming data according to the determined programming mode. Consequently, the loss of programmed data is prevented through an SMD reflow process. | 11-21-2013 |