Patent application number | Description | Published |
20090052264 | Refresh characteristic testing circuit and method for testing refresh using the same - A refresh characteristic test circuit is provided, in a recessed semiconductor device, that is capable of verifying whether a refresh failure is caused by the neighbor/passing gate effect or not and a method for testing the refresh characteristic. The refresh characteristic test circuit includes a select signal generating unit for receiving first address signals and a test mode signal and generate select signals to select cell blocks, a main word line signal generating unit for receiving second address signals and the test mode signal and generate main word lines signals to select main word lines of the selected cell block, and a sub word line signal generating unit for receiving third address signals and the test mode signal and enable sub word lines of the selected main word line. | 02-26-2009 |
20090303810 | Semiconductor memory device - Disclosed is a semiconductor memory device. The semiconductor memory device includes a signal generating unit for generating first and second enable signals in response to a power-up signal, a first sub-word line signal driving unit for driving a first sub-word line signal in response to the first enable signal, a first voltage supplying unit for supplying a first voltage to a pair of bit lines in response to the first enable signal, a second sub-word line signal driving unit for driving a second sub-word line signal in response to the second enable signal, and a second voltage supplying unit for supplying a second voltage to a pair of bit lines in response to the second enable signal. | 12-10-2009 |
20110029143 | REPAIR CIRCUIT INCLUDING REPAIR CONTROLLER - A repair circuit having a repair controller which is capable of reducing unnecessary current dissipation by interrupting a control operation to redundant cells that are unused for replacement of defective cells is presented. The repair circuit includes a repair controller and a repair signal generator. The repair controller is configured to generate a first drive voltage, a second drive voltage and a repair control signal depending on whether or not a defective cell exists. The repair signal generator driven by the first and second drive voltages in which the repair signal generator is configured to generate a repair signal, for repairing the defective cell, in response to receiving the repair control signal and an external address. | 02-03-2011 |
20110158022 | SEMICONDUCTOR MEMORY DEVICE HAVING A REDUCED NOISE INTERFERENCE - A semiconductor memory device having a reduced noise interference is presented. The semiconductor memory device includes a first switch and a second switch. The first switch is disposed in a sub hole region or an edge region and is configured to be turned on in response to a first pre-control signal, which is enabled before a time point at which a sense amplifier array begins to operate, and to apply an external voltage to a first voltage line through which a bias voltage is supplied to the sense amplifier array. The second switch is configured to be turned on in response to a first control signal, which is enabled in a sense amplifier overdriving period, and to apply the external voltage to the first voltage line. | 06-30-2011 |
20150043297 | ACTIVE CONTROL DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An active control device and a semiconductor device including the same are disclosed, which can control an active command in response to a pin change of a command address. The active control device includes: a bank decoding unit configured to decode a bank address to output a bank selection signal; an active controller configured to output a first active control signal, a second active control signal, and an active delay signal to control an active operation of a bank in response to the bank selection signal, a first active signal, and a second active signal; an address latch unit configured to latch a row address to output an address delay signal; and an address output unit configured to output an address corresponding to the address delay signal. | 02-12-2015 |
20150380060 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first cell array region disposed adjacent to a second cell array region; a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; and second group segment input/output lines disposed to correspond to the second cell to array region when viewed in terms of the dummy bit lines. | 12-31-2015 |
20150380070 | LATCH CIRCUIT AND INPUT/OUTPUT DEVICE INCLUDING THE SAME - A latch circuit includes an input block configured to latch first group input addresses and second group input addresses and output first group internal addresses, according to states of select signals; and a latch block configured to latch the first group internal addresses corresponding to a first active command when a first active control signal is activated, and output the first group internal addresses and second group internal addresses as row addresses corresponding to a second active command when a second active control signal is activated. | 12-31-2015 |
20160086644 | SEMICONDUCTOR DEVICE - A semiconductor device includes a clock shifter configured to shift an active control signal by a predetermined number of clocks and output a shift signal according to a test signal; a command selection block configured to select any one of the active control signal and the shift signal according to the test signal, and output an active command signal; an active control block configured to control an active state of a bank active signal according to the active command signal; and an address latch block configured to latch an internal address according to the active command signal and the active control signal, and output a row address to a core region. | 03-24-2016 |
20160086649 | SMART REFRESH DEVICE - A smart refresh device includes an address control block configured to determine whether a specific row address is a row hammer address, and invert a first row hammer address and perform an addition/subtraction of an address; a repair control block configured to determine whether the row hammer address is a repaired address and output a stored repair address as a second repair control signal; a repair address storage block configured to store an output address of the address control block and output a stored address as a latch address; a fuse block configured to output a repair signal representing information on a repair address to the repair control block, and output a decoding signal according to the latch address; and an operator configured to add and subtract the decoding signal according to an addition signal and a subtraction signal. | 03-24-2016 |