Patent application number | Description | Published |
20090052241 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - In a method of operating a non-volatile memory device, a bit line is precharged to a positive voltage, which is input through a common source line of cell strings of memory cells, according to a degree in which a selected memory cell has been programmed. Data according to a voltage level of a sensing node, which is changed according to a level of the voltage of the bit line, is stored in a first latch of a page buffer. The data stored in the first latch is transferred to a second latch through the sensing node. | 02-26-2009 |
20090067254 | NON-VOLATILE MEMORY DEVICE AND A METHOD OF PROGRAMMING A MULTI LEVEL CELL IN THE SAME - A method of programming a multi level cell in a non-volatile memory device includes providing different data to main cells and indicator cells. The main cells and indicator cells have different threshold voltages in accordance with the data. A program operation is performed on a main cell and an indicator cell. A first verifying operation is performed based on a first verifying voltage of the main cell and the indicator cell. The program operation and the first verifying operation are performed repeatedly until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage. A second verifying operation is performed on the main cell based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage. | 03-12-2009 |
20110026325 | METHOD OF PROGRAMMING A MULTI LEVEL CELL - A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage. | 02-03-2011 |
20140160864 | SEMICONDUCTOR DEVICE INCLUDING CURRENT COMPENSATOR - The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line. | 06-12-2014 |
Patent application number | Description | Published |
20100046289 | METHOD OF READING NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of reading a nonvolatile memory device may include, after an n | 02-25-2010 |
20100046293 | MEMORY CELL BLOCK OF NONVOLATILE MEMORY DEVICE AND METHOD OF MANAGING SUPPLEMENTARY INFORMATION - A nonvolatile memory device of a nonvolatile memory device includes a memory cell unit comprising sets of memory cells, a first supplementary information repository comprising source-side dummy cells respectively connected between source select transistors and first memory cells of the sets of the memory cells, and a second supplementary information repository comprising drain-side dummy cells respectively connected between drain select transistors and second memory cells of the sets of the memory cells. | 02-25-2010 |
20100142277 | PAGE BUFFER CIRCUIT, NONVOLATILE MEMORY DEVICE INCLUDING THE PAGE BUFFER CIRCUIT, AND METHOD OF OPERATING THE NONVOLATILE MEMORY DEVICE - A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line. | 06-10-2010 |
20110122707 | PAGE BUFFER CIRCUIT, NONVOLATILE MEMORY DEVICE INCLUDING THE PAGE BUFFER CIRCUIT, AND METHOD OF OPERATING THE NONVOLATILE MEMORY DEVICE - A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line. | 05-26-2011 |
20110128783 | METHOD OF READING NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of reading a nonvolatile memory device may include, after an n | 06-02-2011 |
20130307611 | MULTI-CHIP PACKAGE AND OPERATING METHOD THEREOF - A multi-chip package includes first and second semiconductor chips each configured to perform first and second operations having different current consumptions. The first and second semiconductor chips perform the first operation in response to an enable control signal transmitted from one of the first and second semiconductor chips to the other and transmitted from the other back to the one. | 11-21-2013 |
20140258611 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit. A control circuit is configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, and perform the program operation and update the second storage unit with the externally inputted page address if the externally input page address is greater than the page address loaded into the second storage unit. | 09-11-2014 |