Patent application number | Description | Published |
20090052075 | Systems and Methods for Improved Synchronization Between an Asynchronously Detected Signal and a Synchronous Operation - Various embodiments of the present invention provide systems and methods for synchronizing data processing. As one example, a method for synchronizing data processing is disclosed that includes receiving a data input, and sampling the data input at a sample period to generate a sample set. A first pattern is received and a first periodic boundary associated with the first pattern is identified. In one particular case, the first pattern is a preamble pattern included as sector data on a storage medium, and the first periodic boundary is a 4T boundary. Further, a second pattern is detected in the sample that is used to establish a second periodic boundary. In one particular case, the second pattern is a SAM pattern included as sector data on a storage medium, and the second periodic boundary is a 1T boundary. Based at least in part on the first periodic boundary and the second periodic boundary, a time to transmit or assert a data-found signal is determined. | 02-26-2009 |
20090052602 | Systems and Methods for Improved Timing Recovery - Various embodiments of the present invention provide systems and methods for improved timing recovery. As one example, some embodiments of the present invention provide timing recovery circuits that include an error signal and a digital phase lock loop circuit. The error signal indicates a difference between the predicted sample time and an ideal sample time. The digital phase lock loop is operable to apply an adjustment value such that a subsequent sample time is moved toward the ideal sample time. Further, the digital phase lock loop circuit includes an adjustment limit circuit that is operable to limit the adjustment value. | 02-26-2009 |
20090267819 | Systems and Methods for Reducing the Effects of ADC Mismatch - Various embodiments of the present invention provide systems and methods for utilizing a plurality of potentially mismatched analog to digital converters. For example, a method for adaptively processing a variety of input signals is disclosed. The method includes providing an adaptive loop circuit, and a first and second circuit pairs. The first circuit pair includes a first analog to digital converter and first register, and the second circuit pair includes a second analog to digital converter and a second register. An input signal is received and an event status is received. The event status initially indicates that the input signal includes data associated with a first event and subsequently indicates that the input signal includes data associated with a second event. The first circuit pair to drive the adaptive loop circuit when the first event is indicated, and the second circuit pair to drive the adaptive circuit when the second event is indicated. | 10-29-2009 |
20090268322 | Systems and Methods for Acquiring Modified Rate Burst Demodulation in Servo Systems - Various embodiments of the present invention provide systems and methods for performing modified rate burst demodulation. For example, a method for performing modified rate burst demodulation is disclosed. The method includes receiving a data input that includes a synchronization pattern, an information pattern, and a demodulation pattern. A periodic boundary is established along with a phase and frequency of a sampling clock based at least in part on the synchronization pattern. The information pattern is processed using the sampling clock to determine a location fix. The sampling clock is phase shifted by a skew amount and a phase shifted sampling clock is provided. The demodulation pattern is processed using the phase shifted sampling clock. | 10-29-2009 |
20100142078 | Systems and Methods for Memory Efficient Repeatable Run Out Processing - Various embodiments of the present invention provide systems and methods for low overhead disk wobble compensation. As an example, a method for performing synchronous wobble compensation processing is disclosed. The method includes providing a medium that includes a servo data region and a user data region. The servo data region includes a clock recovery pattern and a location pattern. A detectable pattern is written to the user data region a known number of bit periods from the location pattern. The detectable pattern is read back, and a fractional processing delay is calculated. Based at least on the fractional processing delay and a known number of bit periods from the location pattern to the end of the servo data region, a wobble compensation pattern is written an integral number of bit periods from the location pattern. | 06-10-2010 |
20100177430 | Systems and Methods for Fly-Height Control Using Servo Address Mark Data - Various embodiments of the present invention provide systems and methods for determining fly-height adjustments. For example, various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly disposed in relation to the storage medium ( | 07-15-2010 |
20100232046 | Methods and Systems for Estimating Time Corresponding to Peak Signal Amplitude - Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude. | 09-16-2010 |
20110043938 | Systems and Methods for Fly-Height Control Using Servo Data - Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium having servo data thereon. A read/write head assembly is disposed in relation to the storage medium. A servo based fly-height adjustment circuit receives the servo data via the read/write head assembly, and calculates a first harmonics ratio based on the received data and compares the first harmonics ratio with a second harmonics ratio to determine an error in the distance between the read/write head assembly and the storage medium. | 02-24-2011 |
20110157737 | Systems and Methods for Detecting a Reference Pattern - Various embodiments of the present invention provide systems and methods for locating a reference pattern on a storage medium. For example, various embodiments of the present invention provide systems for locating a reference pattern on a storage medium. Such systems include a sliding window phase calculator circuit, a delay circuit and a mark detector circuit. | 06-30-2011 |
20120026620 | METHODS AND APPARATUS FOR GAIN ESTIMATION USING SERVO DATA WITH IMPROVED BIAS CORRECTION - Methods and apparatus are provided for gain estimation using servo data with improved bias correction. The gain is estimated using a preamble in a servo sector by obtaining a first gain estimate using a first gain estimation algorithm (such as a Zero Gain Start Algorithm) and a first portion of the preamble; storing the first portion of the preamble in a memory buffer; obtaining a second gain estimate using a second gain estimation algorithm (such as a Zero Forcing algorithm) and the first portion of the preamble; and processing Servo Address Mark (SAM) and Gray data in the servo sector using the first gain estimate substantially simultaneous to the step of obtaining the second gain estimate. A gain error can be obtained by calculating a difference between the first gain estimate and the second gain estimate. The gain error can be used in burst processing of the servo data. | 02-02-2012 |
20120036173 | Systems and Methods for Sequence Detection in Data Processing - Various embodiments of the present invention provide systems and methods for sequence detection. As an example, a method for data detection is disclosed that includes: receiving a series of data samples at a detector circuit; multiplying a portion of the series of data samples by a first correlator value corresponding to a first binary transition to yield a first value; multiplying the portion of the series of data samples by a second correlator value corresponding to a second binary transition to yield a second value; adding the first value to a prior state value to yield a first interim value; adding the second value to the prior state value to yield a second interim value; and selecting the larger of the first interim value and the second interim value to yield a surviving interim value. | 02-09-2012 |
20120134042 | Systems and Methods for Signal Polarity Determination - Various embodiments of the present invention provide systems and methods for determining head polarity. As an example, a head polarity detection circuit includes: a first computation circuit, a second computation circuit, and an inversion determination circuit. The first computation circuit is operable to sum an absolute value of each sample of a first subset of a series of data samples corresponding to a first phase of an analog input to yield a first sum, and the second computation circuit is operable to sum an absolute value of each sample of a second subset of the series of data samples corresponding to a second phase of the analog input to yield a second sum. The first phase is more than ninety degrees offset from the second phase. | 05-31-2012 |
20120134043 | Systems and Methods for Spiral Waveform Detection - Various embodiments of the present invention provide systems and methods for determining a location of a spiral pattern. As an example, a location detection circuits is discussed that includes: a pattern detection circuit, a computation circuit, and a center determination circuit. The pattern detection circuit is operable to identify a subset of a series of data samples corresponding to a defined pattern, and to indicate a location of the identified subset of the series of data samples. The series of data samples corresponds to a spiral pattern. The computation circuit operable to sum an absolute value of each sample of the subset of the series of data samples to yield a sum. The center determination circuit operable to identify a location of the spiral pattern using the sum. | 05-31-2012 |
20120155587 | Systems and Methods for Improved Timing Recovery - Various embodiments of the present invention provide systems and methods for timing recovery. As an example, timing recovery circuits include: a first digital interpolation circuit, a second digital interpolation circuit, a phase selection circuit, and a sampling clock rotation circuit. The first digital interpolation circuit is operable to receive a data input and to provide a first interpolated output corresponding to a first phase, and the second digital interpolation circuit is operable to receive the data input and to provide a second interpolated output corresponding to a second phase. The phase selection circuit operable to select the first phase for processing, and the sampling clock rotation circuit is operable to move a sampling clock away from the first phase. | 06-21-2012 |
20120182643 | Systems and Methods for Reduced Format Data Processing - Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier circuit, an analog to digital conversion circuit, a cosine component calculation circuit, a sine calculation circuit, and a zero gain start calculation circuit. The variable gain amplifier circuit is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The analog to digital conversion circuit is operable to convert the amplified output to a corresponding series of digital samples. The cosine component calculation circuit is operable to calculate a cosine component from the series of digital samples, and the sine component calculation circuit operable to calculate a sine component from the series of digital samples. The zero gain start calculation circuit is operable to calculate a raw gain error value based on the cosine component and the sine component, where the gain feedback value is derived from the raw gain error value. | 07-19-2012 |
20120197920 | SYSTEMS AND METHODS FOR DIVERSITY COMBINED DATA DETECTION - Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits including a pattern detection circuit having at least two data detector circuits each operable to receive the same series of data samples and to provide a first detected data output and a second detected data output, respectively. In addition, the data pattern detection circuit includes a result combining circuit that is operable to assert a pattern found output based at least in part on the first detected data output and the second detected data output. | 08-02-2012 |
20120303327 | Systems and Methods for Pattern Detection - Various embodiments of the present invention provide systems and methods related to pattern detection. As an example, a system for sample selection is disclosed that includes a difference calculation circuit, a comparator circuit, and an output selector circuit. The difference calculation circuit is operable to calculate a first difference between a first value corresponding to a first digital sample and a second value corresponding to a second digital sample, and to calculate a second difference between a third value corresponding to a third digital sample and a fourth value corresponding to a fourth digital sample. The comparator circuit is operable to compare the first difference with the second difference to yield a comparison output. The output selector circuit is operable to select one of the second value and the fourth value as an output based at least upon the comparison output. | 11-29-2012 |
20130107687 | METHODS AND APPARATUS FOR VALIDATING DETECTION OF RRO ADDRESS MARKS | 05-02-2013 |
20140029129 | METHODS AND APPARATUS FOR IMPROVED DETECTION OF SERVO SECTOR DATA USING SINGLE BIT ERROR CORRECTION - Methods and apparatus are provided for improved detection of servo sector data in a magnetic recording system using single bit error correction. Servo sector data is processed by detecting the servo sector data; determining whether a single bit error occurred in the detected servo sector data; and flipping a bit value of an individual bit in the detected servo sector data having a lowest amplitude sample among the samples of the detected servo sector data when a single bit error is detected in the detected servo sector data. The servo sector data comprises, for example, a servo address mark, Gray data, an RRO address mark and/or RRO data. For example, the bit value can be flipped by changing a binary value of one to a binary value of zero and changing a binary value of zero to a binary value of one. | 01-30-2014 |
20140033000 | FLAW SCAN CIRCUIT FOR REPEATABLE RUN OUT (RRO) DATA - Improved flaw scan circuits are provided for repeatable run out data. RRO (repeatable run out) data is processed by counting a number of RRO data bits detected in a servo sector; and setting an RRO flaw flag if at least a specified number of RRO data bits is not detected in the server sector. The RRO flaw flag can also optionally be set by detecting an RRO address mark in the servo sector; counting a number of samples in the servo sector after the RRO address mark that do not satisfy a quality threshold; and setting the RRO flaw flag when the counted number of samples that that do not satisfy the quality threshold exceeds a specified flaw threshold. If the RRO flaw flag is set, the RRO data can be discarded, and/or an error recovery mechanism can be implemented to obtain the RRO data. | 01-30-2014 |
20140204987 | System and Method for Determining Channel Loss in a Dispersive Communication Channel at the Nyquist Frequency - The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver based on the normalized Nyquist energy. | 07-24-2014 |
20140241478 | Timing Phase Estimation for Clock and Data Recovery - In order to initialize the phase of the recovered clock signal used in clock-and-data recovery (CDR) circuitry, the normal, on-line CDR processing is disabled. The sum of the absolute values of analog-to-digital converter (ADC) samples are generated for different clock phases over each unit interval (UI) of the analog signal sampled by the ADC for a specified period of time. The phase corresponding to the maximum sum is selected as the initial phase for the recovered clock signal for enabled, on-line CDR processing, which among other things, automatically updates the clock phase to ensure that the ADC samples the analog signal near the center of each UI. | 08-28-2014 |
20140269888 | ADAPTIVE CONTINUOUS TIME LINEAR EQUALIZER - An apparatus comprising an equalizer circuit, a converter circuit and an adaptation circuit. The equalizer circuit may be configured to generate an intermediate signal in response to an input signal and a gradient value. The converter circuit may be configured to generate a digital signal comprising a plurality of symbol values, including a main cursor symbol value, in response to the intermediate signal. The adaptation circuit may be configured to generate the gradient value in response to a plurality of the symbol values before the main cursor symbol value, a plurality of symbol values after the main cursor symbol value, and an error value. | 09-18-2014 |
20150016497 | CLOCK AND DATA RECOVERY ARCHITECTURE WITH ADAPTIVE DIGITAL PHASE SKEW - In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation filter bank by a phase skew adaptation loop, and updating the phase skew values to generate a resulting decision. A device includes a first interpolation filter bank inserted between the equalization stages is configured to generate phase skew signals to a last equalization stage and a phase skew loop responsive to the last equalization stage is configured to adjust the phase skew provided by the first interpolation filter bank. | 01-15-2015 |