Patent application number | Description | Published |
20140131760 | LIGHT EMITTING DEVICE AND MANUFACTURE METHOD THEREOF - A flip-chip LED including a light emitting structure, a first dielectric layer, a first metal layer, a second metal layer, and a second dielectric layer is provided. The light emitting structure includes a first conductive layer, an active layer, and a second conductive layer. The active layer is disposed on the first conductive layer, and the second conductive layer is disposed on the active layer. The first metal layer is disposed on the light emitting structure and is contact with the first conductive layer, and part of the first metal layer is disposed on the first dielectric layer. The second metal layer is disposed on the light emitting structure and is in contact with the second conductive layer, and part of the second metal layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The first conductive layer includes a rough surface so as to improve a light extraction efficiency. | 05-15-2014 |
20140186979 | LIGHT EMITTING DEVICE AND MANUFACTURE METHOD THEREOF - The present disclosure provides a method for forming a light-emitting apparatus, comprising providing a first board having a plurality of first metal contacts, providing a substrate, forming a plurality of light-emitting stacks and trenches on the substrate, wherein the light-emitting stacks are apart from each other by the plurality of the trenches, bonding the light-emitting stacks to the first board, forming an encapsulating material commonly on the plurality of the light-emitting stacks, and cutting the first board and the encapsulating material to form a plurality of chip-scale LED units. | 07-03-2014 |
Patent application number | Description | Published |
20080257375 | BOBBY PIN - A bobby pin includes a left body and a right body respectively having plural ribs that are formed with plural teeth for engaging with each other to keep hair firmly clamped. The left and the right body have an opening device that is provided with a root member respectively, with a pivotal pin mounted with a compression spring and a torsion spring. In using, press inward the two bodies to keep the teeth engaged with each other for clamping hair. And, as long as the opening device is pressed, the two bodies can be immediately separated from each other for releasing hair. | 10-23-2008 |
20090114241 | BOBBY PIN - A bobby pin includes a clamping ribs unit and a hair fork. The clamping rib unit consists of a left and a right clamping rib member interspaced, and the left and the right clamping rib member have a press grip with a shaft hole and a guiding groove. The hair fork has two rods extending from a base member. A shaft stands on the base member, extending in the shaft hole of the press grips with a spring fitted around the shaft. In using, a user presses the two press grips to open the left and the right clamping rib member, with the rods of the hair fork shifted and located in the center of the bobby pin. Then the user inserts the left and the right clamping rib member in hair, with the press grips released to permit the left and the right clamping rib member closed up for clamping hair together with the hair fork. | 05-07-2009 |
20090183751 | HAIR HOOP - A hair hoop includes a plurality of bodies having their opposite ends respectively and pivotally combined together by a support shaft. Thus, with the support shafts acting as fulcrums, each body can freely be turned and moved to different locations of a person's hair for completely tidily binding the hair stably together, able to keep the hair orderly and serve as ornaments. | 07-23-2009 |
20110023906 | ELASTIC HAIR CLIP - An elastic hair clip includes a clip frame composed of a first clip frame and a second clip frame, and a joint member. The first and the second clip frame have one end forming a jointed end and another end forming an open end. A clipping strip is disposed between the first and the second clip frame, a little shorter than the first and the second clip frame and having one end formed integrally with the jointed end of the first and the second clip frame. The joint member can be integrally formed with or separated from the clip frame. When the hair clip is used, the open end of the first and the second clip frame is combined together by the joint member to make the first and the second clip frame properly curved and form proper elasticity for clipping hair with the help of the clipping strip. | 02-03-2011 |
20110297179 | HAIR CLIP - A hair clip includes a main body provided with plural holes, which can be respectively inserted by a small bunch of hair so that a user is able to make a great diversity of hair styles, advancing practicality a lot. | 12-08-2011 |
Patent application number | Description | Published |
20090291614 | FRISBEE STRUCTURE - A frisbee structure, having a piercing hole on the central part, comprises a spinning structure, which further comprises an upper coupling member, a lower coupling member, a fastener and a revolving component. The upper coupling member is arranged on one end of a fastener, the other end of the fastener is hooked up with the revolving component and the lower hook portion on one end of the revolving component is hooked up with the lower coupling member. The assembly of the spinning structure and the frisbee is to enable the upper coupling member to be separated from one end of the fastener, enable that end of the fastener to be corresponding to the piercing hole on the frisbee, and then enable the upper coupling member to be buckled and positioned on the other side of the piercing hole of the Frisbee and formed in one piece with the frisbee. A floating ornament is positioned on one end of the spinning structure assembled on the frisbee, providing more amusements for a player when the frisbee is tossed to produce a rapid spinning action. | 11-26-2009 |
20100276881 | Entertaining Balancing Ball Set - An improved entertaining balancing ball set includes a basis ball of a pre-determined outer diameter and a rolling ball of a smaller diameter. The basis ball includes one or more grooved orbits of which the shape could be branching, labyrinth-like, curving, extending, etc. The grooved orbits include a skewed side, one or more traps, a starting point on one end for each of grooved orbits, and a destination on the other end for each of grooved orbits. The rolling ball has a diameter that is determined based on the width of the groove orbits over which the rolling ball is to move within. The inside of the basis ball could be either hollow or solid. | 11-04-2010 |
20110081812 | Self-supporting Marker Buoy - A self-supporting marker buoy includes an upper unit, a lower unit, and a rim-engaging cover. The upper unit is a frustum which further includes a base opening facing downwards, a hollow center, and a base rim around the base opening. The lower unit is an upside-down frustum, which further includes a top opening facing upwards, a hollow center, a top rim around the top opening, and a water entry at the bottom of the lower unit. The radius of the base opening of the upper unit is less than that of the top opening of the lower unit. | 04-07-2011 |
Patent application number | Description | Published |
20110128796 | DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL - A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line. | 06-02-2011 |
20110235444 | SRAM WRITING SYSTEM AND RELATED APPARATUS - SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal. | 09-29-2011 |
20120008377 | STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY - A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit. | 01-12-2012 |
20120057399 | ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF - The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system. | 03-08-2012 |
20130222071 | Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability - The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately. | 08-29-2013 |
20130223136 | SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor - The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM. | 08-29-2013 |
20140078818 | STATIC RANDOM ACCESS MEMORY WITH RIPPLE BIT LINES/SEARCH LINES FOR IMROVING CURRENT LEAKAGE/VARIATION TOLERANCE AND DENSITY/PERFORMANCE - A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line. | 03-20-2014 |
Patent application number | Description | Published |
20100148253 | HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH SCHOTTKY DIODES - High voltage semiconductor devices with Schottky diodes are presented. A high voltage semiconductor device includes an LDMOS device and a Schottky diode device. The LDMOS device includes a semiconductor substrate, a P-body region in a first region of the substrate, and an N-drift region in the second region of the substrate with a junction therebetween. A patterned isolation region defines an active region. An anode electrode is disposed on the P-body region. An N | 06-17-2010 |
20100163989 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region. | 07-01-2010 |
20100187566 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 07-29-2010 |
20100207174 | SEMINCONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type substrate by a doping process using a mask. The second type bar doped regions are diffused to form a second type continuous region by annealing. The second type continuous region is adjoined with the first type well regions. A second type dopant concentration of the second type continuous region is smaller than a second type dopant concentration of the second type bar doped regions. A second type source/drain region is formed in the second type well region. | 08-19-2010 |
20100301385 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device including a substrate, a first doped region, a first gate electrode, a second doped region, a second gate electrode, and a third doped region is disclosed. The substrate has a first conductive type. The first doped region has a second conductive type and is formed in the substrate. The first gate electrode is formed on the substrate. The second doped region has the second conductive type and is formed in the substrate. A transistor is constituted by the first doped region, the first gate electrode, and the second doped region. The second gate electrode is formed on the substrate. The first and the second gate electrodes are separated. The third doped region has the first conductive type and is formed in the substrate. A discharge element is constituted by the first doped region, the second gate electrode, and the third doped region. | 12-02-2010 |
20100301388 | SEMICONDUCTOR DEVICE AND LATERAL DIFFUSED METAL-OXIDE-SEMICONDUCTOR TRANSISTOR - The invention provides a semiconductor device and a lateral diffused metal-oxide-semiconductor transistor. The semiconductor device includes a substrate having a first conductive type. A gate is disposed on the substrate. A source doped region is formed in the substrate, neighboring with a first side of the gate, wherein the source doped region has a second conductive type different from the first conductive type. A drain doped region is formed in the substrate, neighboring with a second side opposite to the first side of the gate. The drain doped region is constructed by a plurality of first doped regions with the first conductive type and a plurality of second doped regions with the second conductive type, wherein the first doped regions and the second doped regions are alternatively arranged. | 12-02-2010 |
20110198692 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region. A second conductivity type diffused source is disposed on the first conductivity type substrate outside of the second sidewall. A second conductivity type diffused drain is disposed on the second conductivity type well region outside of the first sidewall. First conductivity type buried rings are arranged in a horizontal direction, separated from each other, and formed in the second conductivity type well region. Doped profiles of the first conductivity type buried rings gradually become smaller in a direction from the second conductivity type diffused source to the second conductivity type diffused drain. | 08-18-2011 |
20110233672 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region. | 09-29-2011 |
20120001225 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 01-05-2012 |
20120175727 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer. | 07-12-2012 |
20120190169 | METHOD FOR FABRICATING DEEP TRENCH ISOLATION - The invention provides a method for fabricating a deep trench isolation including: providing a substrate; forming a first trench in the substrate; conformally forming a first liner layer on the sidewall and bottom of the first trench; forming a first filler layer on the first liner layer and filling the first trench; forming an epitaxial layer on the substrate and the first trench; forming a second trench through the epitaxial layer and over the first trench; conformally forming a second liner layer on the sidewall and bottom of the second trench; and forming a second filler layer on the second liner layer and filling the second trench. | 07-26-2012 |
20120223383 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region. | 09-06-2012 |
20120231598 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region. | 09-13-2012 |
20130175607 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device is provided. The semiconductor device includes a substrate having a first doping region and an overlying second doping region, wherein the first and second doping regions have a first conductivity type and wherein the second doping region has at least one first trench and at least one second trench adjacent thereto. A first epitaxial layer is disposed in the first trench and has a second conductivity type. A second epitaxial layer is disposed in the second trench and has the first conductivity type, wherein the second epitaxial layer has a doping concentration greater than that of the second doping region and less than that of the first doping region. A gate structure is disposed on the second trench. A method of fabricating a semiconductor device is also disclosed. | 07-11-2013 |
20130175608 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device is provided. The semiconductor device includes a plurality of first epitaxial layers, a second epitaxial layer and a gate structure. The plurality of first epitaxial layers is stacked on a substrate and has a first conductivity type. Each first epitaxial layer includes at least one first doping region and at least one second doping region adjacent thereto. The first doping region has a second conductivity and the second doping region has the first conductivity type. The second epitaxial layer is disposed on the plurality of first epitaxial layers, having the first conductivity type. The second epitaxial layer has a trench therein and a third doping region having the second conductivity type is adjacent to a sidewall of the trench. The gate structure is disposed on the second epitaxial layer above the second doping region. A method of fabricating a semiconductor device is also disclosed. | 07-11-2013 |
20140035029 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial layer of the first conductivity type disposed thereon is disclosed. Pluralities of first and second trenches are alternately arranged in the epitaxial layer. First and second doped regions of the first conductivity type are formed in the epitaxial layer and surrounding each first trench. A third doped region of a second conductivity type is formed in the epitaxial layer and surrounding each second trench. A first dopant in the first doped region has diffusivity larger than that of a second dopant in the second doped region. A method for fabricating a semiconductor device is also disclosed. | 02-06-2014 |
Patent application number | Description | Published |
20090027245 | METHOD OF GAIN ERROR CALIBRATION IN A PIPELINED ANALOG-TO-DIGITAL CONVERTER OR A CYCLIC ANALOG-TO-DIGITAL CONVERTER - The invention provides a method of gain error calibration in a pipelined analog-to-digital converter (ADC). In one embodiment, a first stage and a second stage of the pipelined ADC share a common operational amplifier. The first stage is requested to generate the stage output signal thereof according to a first correction number. The second stage is also requested to generate the stage output signal thereof according to a second correction number. A plurality of stage output values generated by stages of the pipelined ADC are collected. The stage output values are respectively correlated with the first correction number and the second correction number to estimate a first gain error estimate of the first stage and a second gain error estimate of the second stage. The first gain error estimate and the second gain error estimate are weighted to obtain a predicted gain error for gain error calibration in the first stage and the second stage. | 01-29-2009 |
20090027246 | ANALOG-TO-DIGITAL CONVERTER AND METHOD OF GAIN ERROR CALIBRATION THEREOF - The invention provides an analog-to-digital converter (ADC). The ADC comprises a plurality of stages connected in series, a gain error correction module, and a look-ahead module. Each of the stages derives a stage output value from a stage input signal and generates a stage output signal as the stage input signal of a subsequent stage, wherein one of the stages is selected as a target stage for estimating a gain value thereof. The gain error correction module delivers a correction number to the target stage to affect the stage output signal of the target stage and the stage output values of subsequent stages of the target stage, receives at least one auxiliary output value from a look-ahead module dedicated to the target stage, and derives an error estimate of the gain value of the target stage from the stage output values and the auxiliary output value. The look-ahead module generates the auxiliary output value according to the stage output value of the target stage, wherein the auxiliary output value is not affected by the correction number. | 01-29-2009 |
20090051574 | METHOD FOR GAIN ERROR ESTIMATION IN AN ANALOG-TO-DIGITAL CONVERTER AND MODULE THEREOF - The invention provides a method for gain error estimation in an analog-to-digital converter. In one embodiment, the analog-to-digital converter comprises a plurality of stages. A series of correction numbers applied to a target stage selected from the stages are correlated with a series of calculation values calculated according to digital output values of the stages to generate a series of gain error estimates. The series of gain error estimates are multiplied by a series of updating parameters to obtain a series of first values. A series of previous gain error values are multiplied by one minus the corresponding updating parameters to obtain a series of second values, wherein the series of previous gain values are obtained by delaying the present gain error values. The series of first values and the series of second values are correspondingly added to obtain a series of present gain error values for gain error correction. | 02-26-2009 |
20090055127 | METHOD FOR GAIN ERROR ESTIMATION FOR AN ANALOG-TO-DIGITAL CONVERTER - The invention provides a method for gain error estimation for an analog-to-digital converter. In one embodiment, the analog-to-digital converter comprises a plurality of stages. First, a series of correction numbers applied to a target stage selected from the stages are correlated with a series of first values calculated according to digital output values of the stages to generate a series of gain error estimates. Every first number of the series of gain error estimates is then averaged to obtain a series of second values. A second number of the series of second values is then averaged to obtain a gain error of the target stage. | 02-26-2009 |
20100182056 | METHODS FOR CALIBRATING GATED OSCILLATOR AND OSCILLATOR CIRCUIT UTILIZING THE SAME - An oscillator circuit is provided. The oscillator circuit includes a gated oscillator and a calibration circuit. The gated oscillator is arranged to generate an oscillator signal according to a control signal, and receive a gating signal to align an edge of the oscillator signal with an edge of the gating signal. The calibration circuit coupled to the gated oscillator is arranged to receive a first clock signal and a second clock signal, detect an alignment operation of the gated oscillator according to the first clock signal and a second clock signal and generate the control signal according to the detected alignment operation. | 07-22-2010 |
20110032132 | DELTA-SIGMA ANALOG-TO-DIGITAL CONVERSION APPARATUS AND METHOD THEREOF - A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer. | 02-10-2011 |
20110187571 | DELTA-SIGMA ANALOG-TO-DIGITAL CONVERSION APPARATUS AND METHOD THEREOF - A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer. | 08-04-2011 |