Patent application number | Description | Published |
20090051310 | Closed Loop Stepper Motor Control - System and method for controlling a stepper motor. A current position of the stepper motor may be received. A position error of the stepper motor may be determined using the current position of the stepper motor. A velocity profile may be maintained based on the position error, such that it tracks the position error. A position correction value may be determined based on the velocity profile, e.g., by integrating a portion of the velocity profile. A new position value may be generated to drive the stepper motor. An output position value to the stepper motor may be provided to drive the stepper motor. The output position value may incorporate the new position value and the position correction value and may be operable to reduce position error of the stepper motor. | 02-26-2009 |
20090106755 | Programmable Controller with Multiple Processors Using Scanning and Data Acquisition Architectures - Operating a programmable controller with a plurality of processors. The programmable controller may utilize a first subset of the plurality of processors for a scanning architecture. The first subset of the plurality of processors may be further subdivided for execution of periodic programs or asynchronous programs. The programmable controller may utilize a second subset of the plurality of processors for a data acquisition architecture. Execution of the different architectures may occur independently and may not introduce significant jitter (e.g., for the scanning architecture) or data loss/response time lag (e.g., for the data acquisition architecture). However, the programmable controller may operate according to any combination of the divisions and/or architectures described herein. | 04-23-2009 |
20090106761 | Programmable Controller with Multiple Processors Using a Scanning Architecture - Operating a programmable controller with a plurality of processors. The programmable controller may utilize a first subset of the plurality of processors for a scanning architecture. The first subset of the plurality of processors may be further subdivided for execution of periodic programs or asynchronous programs. The programmable controller may utilize a second subset of the plurality of processors for a data acquisition architecture. Execution of the different architectures may occur independently and may not introduce significant jitter (e.g., for the scanning architecture) or data loss/response time lag (e.g., for the data acquisition architecture). However, the programmable controller may operate according to any combination of the divisions and/or architectures described herein. | 04-23-2009 |
20090144647 | Motion Controller That Supports Standard and Custom Axes - System and method for developing a motion application. A motion manager component implementing a supervisory control function and at least one trajectory generation algorithm is stored on a motion controller. A first application programming interface (API) for interfacing the motion manager component to a user developed motion control application is displayed. A second API for interfacing the motion manager component to a user developed communication interface component is displayed. A user application executable for sequencing motion operations in the motion system is created using the first API is created in response to user input. A first communication interface component is created using the second API in response to user input, where the communication interface component is operable to interface with the motion manager component using the second API, and where the user developed communication interface component is executable to communicate with a motion element, e.g., a drive or simulation. | 06-04-2009 |
20100030539 | Simulation of a Motion System Including a Mechanical Modeler with Interpolation - Simulating a mechanical system controlled by a motion controller. First position data may be received. The first position data may be provided by a motion controller at a first rate. The first position data received at the first rate may be interpolated to provide second position data at a second rate. Operation of the mechanical system may be simulated or modeled using the second position data at the second rate. Interpolating the first position data and modeling the operation of the mechanical system may be performed without simulating drives and motors necessary to drive the mechanical system. | 02-04-2010 |
20100063603 | Adapting Move Constraints for Position Based Moves in a Trajectory Generator - Adapting move constraints for position based moves in a trajectory generator. Specification of a trajectory may be received. The specification may include a geometry of the trajectory, where the geometry specifies a desired trajectory length. A plurality of constraints for the trajectory may be received. The plurality of constraints may include one or more of a velocity, acceleration, or jerk constraint. A motion control profile may be generated based on the plurality of constraints. The method may include determining if a distance of the motion control profile exceeds the desired trajectory length. If the distance of the motion control profile exceeds the desired trajectory length, one or more values of the plurality of constraints may be decreased to make the distance of the motion control profile less than or equal to the desired trajectory length. | 03-11-2010 |
20110022822 | Motion Controller Utilizing a Plurality of Processors - Controlling a motion system using a plurality of processors. First input data may be received which corresponds to a first portion of the motion system. Second input data may be received which corresponds to a second portion of the motion system. Execution of a first function of a plurality of sequential functions may be assigned to a first processor to determine output for the first portion based on the first input data. Execution of the first function may be assigned to a second processor to determine output for the second portion based on the second input data. The first processor executing the first function and the second processor executing the first function may be performed in parallel. The output for the first portion of the motion system may be provided to the first portion. The output for the second portion of the motion system may be provided to the second portion. | 01-27-2011 |
20110182300 | Network Traffic Shaping for Reducing Bus Jitter on a Real Time Controller - System and method for controlling access to a bus. A Network Interface (NI) is coupled to a memory via the bus, and receives a schedule to a Direct Memory Access (DMA) controller on the NI. The schedule indicates one or more timeslots reserved for transmission of deterministic data, and further indicates one or more available timeslots which are not reserved for transmission of deterministic data. The NI receives first data for transmission onto the bus, during a first timeslot of the available timeslots, where the first data are received in a non-deterministic manner, and determines that the first timeslot is a reserved timeslots based on the schedule. The first data are buffered in a buffer memory during the first timeslot, and transferred to the first memory via the bus during a second timeslot after the buffering, where the second timeslot is one of the one or more available timeslots. | 07-28-2011 |
20110288663 | Motion Controller With Standard and User Customized Components - System and method for developing a motion application. A motion manager component implementing a supervisory control function and at least one trajectory generation algorithm is stored on a motion controller. A first application programming interface (API) for interfacing the motion manager component to a user developed motion control application is displayed. A second API for interfacing the motion manager component to a user developed communication interface component is displayed. A user application executable for sequencing motion operations in the motion system is created using the first API is created in response to user input. A first communication interface component is created using the second API in response to user input, where the communication interface component is operable to interface with the motion manager component using the second API, and where the user developed communication interface component is executable to communicate with a motion element, e.g., a drive or simulation. | 11-24-2011 |
20120030495 | Clock Distribution in a Distributed System with Multiple Clock Domains Over a Switched Fabric - System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events. | 02-02-2012 |
20120030496 | Specification of Isochronous Data Transfer in a Graphical Programming Language - System and method for transferring data. A system diagram is displayed, where the system diagram includes multiple device icons corresponding to respective devices, each device icon having associated executable function nodes specified for deployment on the corresponding device. The function nodes are interconnected to form a distributed graphical program that is deployable and executable in a distributed manner on the devices. User input is received to the system diagram specifying isochronous data transfer among the function nodes. Invocation timing relationships among the function nodes are automatically determined based on the specified isochronous data transfer, including phase relationships between execution of the function nodes. The determined invocation timing relationships are displayed among the function nodes. The graphical program is deployable and executable in a distributed manner on the devices according to the determined invocation timing relationships, where during execution of the graphical program, data are transferred isochronously between the function nodes. | 02-02-2012 |
20120030600 | Isochronous Data Transfer in a Graphical Program - System and method for transferring data. A system diagram is displayed, where the system diagram includes multiple device icons corresponding to respective devices, each device icon having associated executable function nodes specified for deployment on the corresponding device. The function nodes are interconnected to form a distributed graphical program that is deployable and executable in a distributed manner on the devices. User input is received to the system diagram specifying isochronous data transfer among the function nodes. Invocation timing relationships among the function nodes are automatically determined based on the specified isochronous data transfer, including phase relationships between execution of the function nodes. The determined invocation timing relationships are displayed among the function nodes. The graphical program is deployable and executable in a distributed manner on the devices according to the determined invocation timing relationships, where during execution of the graphical program, data are transferred isochronously between the function nodes. | 02-02-2012 |
20130080661 | Configuring Buffers with Timing Information - Configuring a buffer with timing information. Initially, a buffer for transferring data from a first device to a second device may be configured, e.g., in response to user input. For example, configuring the buffer may include specifying a size of the buffer, specifying timing for delivery of data of the buffer, and/or specifying transfer of the data from a first device to a second device. In response to the configuration of the buffer, code may be automatically generated which implements the transfer of the data from the first device to the second device according to the specified timing for delivery of the data of the buffer. Accordingly, the automatically generated code may be executable to transfer the data according to the specified timing from the first device to the second device. | 03-28-2013 |
20130198429 | Bus Arbitration for a Real-Time Computer System - In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described. | 08-01-2013 |
20140019794 | Counter Based Clock Distribution in a Distributed System With Multiple Clock Domains Over a Switched Fabric - System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events. | 01-16-2014 |
20140059553 | HARDWARE ASSISTED REAL-TIME SCHEDULER USING MEMORY MONITORING - Apparatus and method for real-time scheduling. An apparatus includes first and second processing elements and a memory. The second processing element is configured to generate or modify a schedule of one or more tasks, thereby creating a new task schedule, and to write to a specified location in the memory to indicate that the new schedule has been created. The first processing element is configured to monitor for a write to the specified location in the memory and execute one or more tasks in accordance with the new schedule in response to detecting the write to the specified location. The first processing element may be configured to begin executing tasks based on detecting the write without invoking an interrupt service routine. The second processing element may store the new schedule in the memory. | 02-27-2014 |
20140071982 | Clock Synchronization Over A Switched Fabric - Devices and methods for synchronizing devices over a switched fabric. A master device maintains a global time, determines a mapping between the global time and a counter of a switch over a memory-mapped fabric, and sends the mapping to a slave device. A slave device maintains a local time, determines a first mapping between the local time and a counter of a switch, receives a second mapping between the counter and a global time of the master device, and synchronizes its local time to the global time based on the first and second mappings. The master and slave device may map their times to the counter by sending respective request packets to the switch and receiving respective completion packets including respective counter values from the switch. The master and slave device may determine respective time values corresponding to the respective counter values based on in-switch delays of the packets. | 03-13-2014 |
20140075235 | Switch for Clock Synchronization Over A Switched Fabric - Devices and methods for synchronizing devices over a switched fabric. A switch receives a request packet from a device, transmits a completion packet to the device, determines an in-switch delay, and stores the in-switch delay. Another switch receives a packet from a first device, forwards the packet to a second device, determines an in-switch delay of the packet, and stores the in-switch delay. Storing of in-switch delays may include adding an in-switch delay to values in one or more transaction delay fields of a packet. Storing of in-switch delays may include storing the delays in a storage element of a switch. In-switch delay may be determined as a difference between a receiving time corresponding to reception of a packet and a forwarding or transmittal time corresponding to forwarding or transmitting of a packet. | 03-13-2014 |
20140101347 | Isochronous Data Transfer Between Memory-Mapped Domains of a Memory-Mapped Fabric - Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating. | 04-10-2014 |
20140109096 | Time Monitoring in a Processing Element and Use - System and method for controlling thread execution via time monitoring circuitry in a processing element. Execution of a thread may be suspended via a thread suspend/resume logic block included in the processing element in response to a received suspend thread instruction. An indication of a wakeup time may be received to a time monitoring circuit (TMC) included in the processing element. Time may be monitored via the TMC using a clock included in the processing element, until the wakeup time obtains. The thread suspend/resume logic block included in the processing element may be invoked by the TMC in response to the wakeup time obtaining, thereby resuming execution of the thread | 04-17-2014 |
20140223055 | Controlling Bus Access in a Real-Time Computer System - In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described. | 08-07-2014 |
20140223056 | Controlling Bus Access Priority in a Real-Time Computer System - In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described. | 08-07-2014 |
20140304709 | Hardware Assisted Method and System for Scheduling Time Critical Tasks - A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task. | 10-09-2014 |