Patent application number | Description | Published |
20080211306 | Method and System for Supplying Power to Multiple Voltage Islands Using a Single Supply Source (SSS) - Methods and systems for supplying power to multiple voltage islands using a single supply source are disclosed. Aspects of one method may include providing power to a first of a plurality of voltage islands, and individually controlling providing of power to each of a remaining portion of the plurality of voltage islands. For example, when an electronic system is first powered on, a low current voltage source may be used to supply power to a primary voltage island. As a higher current voltage source becomes available, power derived from the higher current voltage source may be provided to the primary voltage island and to secondary voltage islands. Power to each of the secondary voltage islands may be, for example, individually controlled via a power MOS transistor. The power MOS transistor may also be configured to allow a faster blocking time than unblocking time. | 09-04-2008 |
20080215787 | Method and System for Processing Status Blocks Based on Interrupt Mapping - Certain aspects of a method and system for processing status blocks based on interrupt mapping may be disclosed. Exemplary aspects of the method may include determining whether a particular status block has been processed by at least one CPU based on comparing a value of a first register with a value of a second register, wherein the first register may comprise a running index value of at least one client segment within the particular status block and the second register may comprise a current running index value of at least one client segment. An interrupt may be generated, if the value of the first register is not equal to the value of the second register. The particular status block may be processed by at least one CPU based on the generated interrupt. | 09-04-2008 |
20080235484 | Method and System for Host Memory Alignment - Certain aspects of a method and system for host memory alignment may include splitting a received read and/or write I/O request at a first of a plurality of memory cache line boundaries to generate a first portion of the received I/O request. A second portion of the received read and/or write I/O request may be split into a plurality of segments so that each of the plurality of segments is aligned with one or more of the plurality of memory cache line boundaries. A cost of memory bandwidth for accessing host memory may be minimized based on the splitting of the second portion of the received read and/or write I/O request. | 09-25-2008 |
20080270599 | METHOD AND SYSTEM FOR CONFIGURING A PLURALITY OF NETWORK INTERFACES THAT SHARE A PHYSICAL INTERFACE - Certain aspects of a method and system for configuring a plurality of network interfaces that share a physical interface (PHY) may include a system comprising one or more physical network interface controllers (NICs) and two or more virtual NICs. One or more drivers associated with each of the virtual NICs that share one or more Ethernet ports associated with the physical NICs may be synchronized based on controlling one or more parameters associated with one or more Ethernet ports. One or more wake on LAN (WoL) patterns associated with each of the drivers may be detected at one or more Ethernet ports. A wake up signal may be communicated to one or more drivers associated with the detected WoL patterns. One of the drivers may be appointed to be a port master driver. If a failure of the appointed port master driver is detected, another driver may be appointed to be the port master driver. | 10-30-2008 |
20080310420 | Method and system for transparent TCP offload with transmit and receive coupling - Certain aspects of a method and system for transparent transmission control protocol (TCP) offload with transmit and receive coupling are disclosed. Aspects of a method may include collecting at least one received TCP segment for a determined network flow via a network interface card (NIC) processor. The state information for the received TCP segment and state information for transmitted TCP segments for the determined network flow may be stored at the NIC without transferring state information for the received TCP segment and the state information for the transmitted TCP segments to a host system communicatively coupled to the NIC. A new TCP segment comprising the collected TCP segments may be generated after a termination event occurs. The generated new TCP segment, new state information for the generated new TCP segment, and the state information for the transmitted TCP segments may be communicated to the host system for TCP offload. | 12-18-2008 |
20090080332 | Method and System for a Fast Drop Recovery for a TCP Connection - Methods and systems for a fast drop recovery for a TCP connection are disclosed. Aspects of one method may include a receiving device on a network receiving an out-of-order data. The receiving device may then signal to a transmitting device on the network, which sent the out-of-order packet, to enter a congestion alleviation mode without waiting for a delay period. The network packet transfer may be via TCP protocol, for example. The delay period may comprise a retransmission time-out period if the receiving device does not save isles. If the receiving device does save one or more isles, the delay period may be a period associated with delayed ACK. The signal may comprise a TCP option and/or an available TCP flag. The signal may also comprise, for example, three duplicate ACKs. Other similar signals may be used for networks that use other protocols than TCP. Upon receiving out-of-order data, the receiving device may, for example, send the signal and then assert a signal-sent flag if it is not already asserted. When a new packet is received in order, the signal-sent flag may be de-asserted. | 03-26-2009 |
20090150702 | CONTROLLING AUXILIARY POWER TO LOGIC DEVICES - Various example implementations are disclosed. According to one example implementation, a system may include multiple logic devices, a power input, and a logic controller. The logic devices may each be configured to assert a request for auxiliary power to a logic controller. The power input may be configured to provide the auxiliary power to one or more of the logic devices. The logic controller may be configured to poll the logic devices by polling less than all of the logic devices at a time to determine whether the logic devices assert the request for the auxiliary power. | 06-11-2009 |
20100174824 | Method and System for Transparent TCP Offload - Certain aspects of a method and system for transparent transmission control protocol (TCP) offload are disclosed. Aspects of a method may include collecting TCP segments in a network interface card (NIC) processor without transferring state information to a host system. The collected TCP segments may be buffered in a coalescer. The coalescer may verify that the network flow associated with the collected TCP segments has an entry in a flow lookup table (FLT). When the FLT is full, the coalescer may close a current entry and assign the network flow to the available entry. The coalescer may also update information in the FLT. When an event occurs that terminates the collection of TCP segments, the coalescer may generate a single aggregated TCP segment based on the collected TCP segments. The aggregated TCP segment and state information may be communicated to the host system for processing. | 07-08-2010 |
20100198984 | Method and System for Transparent TCP Offload with Best Effort Direct Placement of Incoming Traffic - Certain aspects of a method and system for transparent transmission control protocol (TCP) offload with best effort direct placement of incoming traffic are disclosed. Aspects of a method may include collecting TCP segments in a network interface card (NIC) processor without transferring state information to a host processor every time a TCP segment is received. When an event occurs that terminates the collection of TCP segments, the NIC processor may generate a new aggregated TCP segment based on the collected TCP segments. If a placement sequence number corresponding to the generated new TCP segment for the particular network flow is received before the TCP segment is received, the generated new TCP segment may be transferred directly from the memory to the user buffer instead of transferring the data to a kernel buffer, which would require further copy by the host stack from kernel buffer to user buffer. | 08-05-2010 |
20100241725 | ISCSI RECEIVER IMPLEMENTATION - A method for communication is disclosed and may include, in a network interface device, parsing a portion of a TCP segment into one or more portions of Internet Small Computer Systems Interface (iSCSI) Protocol Data Units (PDUs). A header and/or a payload for one or more of the parsed iSCSI PDUs may be recovered. Concurrent with parsing of a remaining portion of the TCP segment to recover a remaining portion of PDUs, the recovered header may be evaluated and/or the recovered payload may be routed external to the network interface device for processing. The evaluating and the routing may occur independently of the parsing within the network interface device. Respective separate physical processors may be used for the parsing and the recovering. The respective separate processors for recovering may be used for the evaluating and the routing. | 09-23-2010 |
20100274549 | DESIGN SIMULATION USING PARALLEL PROCESSORS - A method for design simulation includes partitioning a verification task of a design ( | 10-28-2010 |
20110067016 | EFFICIENT PARALLEL COMPUTATION ON DEPENDENCY PROBLEMS - A computing method includes accepting a definition of a computing task ( | 03-17-2011 |
20110185370 | Method and System for Configuring a Plurality of Network Interfaces That Share a Physical Interface - Certain aspects of a method and system for configuring a plurality of network interfaces that share a physical interface (PHY) may include a system comprising one or more physical network interface controllers (NICs) and two or more virtual NICs. One or more drivers associated with each of the virtual NICs that share one or more Ethernet ports associated with the physical NICs may be synchronized based on controlling one or more parameters associated with one or more Ethernet ports. One or more wake on LAN (WoL) patterns associated with each of the drivers may be detected at one or more Ethernet ports. A wake up signal may be communicated to one or more drivers associated with the detected WoL patterns. One of the drivers may be appointed to be a port master driver. If a failure of the appointed port master driver is detected, another driver may be appointed to be the port master driver. | 07-28-2011 |
20110191092 | PARALLEL SIMULATION USING MULTIPLE CO-SIMULATORS - A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks. | 08-04-2011 |
20120173909 | CONTROLLING AUXILIARY POWER TO LOGIC DEVICES - A system may include multiple logic devices, a power input, and a logic controller. The power input may be configured to provide the auxiliary power to the logic devices. The logic controller may be configured to select a group of the logic devices for disabling the auxiliary power based, at least in part, on priority levels asserted by each of the logic devices, and disable the auxiliary power to the selected group of logic devices. | 07-05-2012 |
20120181863 | Method and System for Supplying Power to Multiple Voltage Islands Using a Single Supply Source (SSS) - Methods and systems for supplying power to multiple voltage islands using a single supply source are disclosed. Aspects of one method may include providing power to a first of a plurality of voltage islands, and individually controlling providing of power to each of a remaining portion of the plurality of voltage islands. For example, when an electronic system is first powered on, a low current voltage source may be used to supply power to a primary voltage island. As a higher current voltage source becomes available, power derived from the higher current voltage source may be provided to the primary voltage island and to secondary voltage islands. Power to each of the secondary voltage islands may be, for example, individually controlled via a power MOS transistor. The power MOS transistor may also be configured to allow a faster blocking time than unblocking time. | 07-19-2012 |
20130263100 | EFFICIENT PARALLEL COMPUTATION OF DEPENDENCY PROBLEMS - A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task. | 10-03-2013 |
20140379320 | DESIGN SIMULATION USING PARALLEL PROCESSORS - A method for design simulation includes partitioning a verification task of a design ( | 12-25-2014 |