Patent application number | Description | Published |
20090319756 | Duplexed operation processor control system, and duplexed operation processor control method - The present invention provides a duplexed operation processor control system that includes operation processors, an I/O device, and at least one communication path that couples the operation processors to the I/O device, and at least one communication path that couples the operation processors with each other. The duplexed operation processor control system switches over either of the operation processors to be a primary operation processor that executes a control operation for a control target, and the other to be a secondary operation processor that is in a stand-by state, and the secondary operation processor snoops control data synchronously when the primary operation processor acquires the control data from the control target. | 12-24-2009 |
20100050062 | SENDING DEVICE, RECEIVING DEVICE, COMMUNICATION CONTROL DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION CONTROL METHOD - The system has, provided in a sending device, a generator generating transmission data including data, a data error detection code generated from the data and a safety flag indicating a degree of reliability, and transmission data; has, provided in a receiving device, a plurality of components of extracting transmission data, a safety flag, and a data error detection code from a received frame, and detecting a data error, a comparator comparing the matching of a plurality of received frames, and a selector selecting one received frame, from the frame error detection result, the safety flag, the data error detection result, and the matching comparison result; and determines the validity of transmitted data by the detection corresponding to the degree of reliability set with the safety flag. | 02-25-2010 |
20100174967 | CONTROL APPARATUS AND CONTROL METHOD - A failure is detected immediately and certainly, and continuation of processing in an unstable state is prevented. A first error detection code is generated from first information which is output as a result of execution of a predetermined program conducted by a first processor. A second error detection code is generated from second information which is output as a result of execution of the program conducted by a second processor which is configured so as to output the same computation result as that of the first processor. It is detected whether the first information is the same as the second information, and it is detected whether the first error detection code is the same as the second error detection code. Writing the first information or the second information into a main memory is controlled on the basis of a result of the detection. | 07-08-2010 |
20110022936 | SENDING DEVICE, RECEIVING DEVICE, COMMUNICATION CONTROL DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION CONTROL METHOD - A receiving device including: a receiver receiving two frames, each including substantially same data attached thereto with a data error detection code, a frame error detection code, and safety flag information indicating a safety function or not, respectively; a first detector connected to the receiver for performing error detection of the frames by use of the frame error detection code, respectively; a second detector connected to the receiver for performing error detection of the data by use of the data error detection code, respectively; and a Direct Memory Access Controller (DMAC) connected to the first and second detectors for outputting one among the data included in the two frames under a condition of the safety function in the two frames when no error is detected in the frame and data error detections. | 01-27-2011 |
20110131348 | CONTROL SYSTEM AND CPU UNIT - In the disclosed control system, loops of 1st path and 2nd path are formed connecting an active CPU unit and each of RIO units, the direction of data frame transfer through the loop of 1st path being opposite to that of the data frame transfer through the loop 2nd path. Reflective electro-optical transducer modules are used in the RIO units which are connected with the active CPU unit so that a standby CPU unit can also be connected. Further, the loop of 1st path and the loop of 2nd path are formed connecting the standby CPU module and each of the RIO modules. The data frame transfer directions through the loops connecting the active CPU unit and each of the RIO units are opposite to the data frame transfer directions through the corresponding loops connecting the standby CPU unit and each of the RIO units. | 06-02-2011 |
20110214125 | TASK MANAGEMENT CONTROL APPARATUS AND METHOD HAVING REDUNDANT PROCESSING COMPARISON - An input/output control apparatus including: a unit that controls input/output of data relating to a computation of a plurality of processors in response to an access request from a second input/output unit and an access request from a first input/output unit which requires higher reliability than said second input/output unit, and orders at least one of a plurality of processors to perform a computation relating to the access request from said first input/output unit away from the computation relating to the access request from said second input/output unit in case of that said first input/output unit issued an access request, so that a same computation is made by said plurality of processors; a unit that compares the results of said computations relative to the access request from said first input/output unit provided from said plurality of processors; and a unit that allows the data associated with said computations of said processors to be output on the basis of said compared results. | 09-01-2011 |
Patent application number | Description | Published |
20090166060 | Insulating Resin Layer, Insulating Resin Layer With Carrier And Multiple-Layered Printed Wiring Board - An insulating resin layer, which is capable of being employed for forming a multiple-layered printed wiring board via a thermal compression forming process, comprising: at least one first layer and at least one second layer being stacked, wherein a specific dielectric constant of the first layer at a frequency of 1 MHz after the thermal compression forming is not more than 3.2, and wherein a linear expansion coefficient of the second layer at a temperature within a range of from not lower than 35 degree C. to not higher than 85 degree C. after the thermal compression forming is not more than 40 ppm/degree C. A multiple-layered printed wiring board, formed by disposing the aforementioned insulating resin layer over at least one side of an internal layer circuit board, and then conducting a thermal compression forming process. | 07-02-2009 |
20100078201 | LAMINATED BODY, CIRCUIT BOARD INCLUDING LAMINATED BODY, SEMICONDUCTOR PACKAGE AND PROCESS FOR MANUFACTURING LAMINATED BODY - There is provided a laminated body comprising a first resin layer consisting of a first fibrous base material and a resin and a second resin layer consisting of a second fibrous base material and a resin, wherein the first resin layer and the second resin layer are disposed such that the first resin layer and the second resin layer are at least partly positioned in separate regions separated by the center line in a thickness direction of the laminated body; wherein at least one of the first fibrous base material and the second fibrous base material has a bowing region where a bowing region is a region in which a smaller warp/weft crossing angle is less than 90° in the fibrous base material; and wherein in the bowing region, an angle formed by a warp of the first fibrous base material and a warp of the second fibrous base material and an angle formed by a weft of the first fibrous base material and a weft of the second fibrous base material, whichever is larger, is 2° or less. | 04-01-2010 |
20110308848 | RESIN COMPOSITION FOR WIRING BOARD, RESIN SHEET FOR WIRING BOARD, COMPOSITE BODY, METHOD FOR PRODUCING COMPOSITE BODY, AND SEMICONDUCTOR DEVICE - Disclosed are a composite body, a method for producing the composite body and a semiconductor device, the composite body comprising a resin layer and a fine wiring and/or via hole being formed in the resin layer, having high adhesion and high reliability, and being capable of high frequencies. Also disclosed are a resin composition and a resin sheet, both of which can provide such a composite body. | 12-22-2011 |
20130242520 | INSULATING SUBSTRATE, METAL-CLAD LAMINATE, PRINTED WIRING BOARD AND SEMICONDUCTOR DEVICE - The present invention provides: an insulating substrate or metal-clad laminate able to sufficiently reduce or prevent negative warping of a semiconductor device; a printed wiring board that uses the insulating substrate or metal-clad laminate; and a semiconductor device. The insulating substrate is composed of a cured product of a laminate including one or more fibrous base material layers and two or more resin layers, in which the outermost layers on both sides is the resin layers. At least one of the fibrous base material layers is shifted towards the first side or a second side on the opposite side thereof with respect to the reference position, namely the dividing position at which a total thickness of the insulating substrate is equally divided by the number of the fibrous base material layers and each divided region having the thickness is further equally divided by two. The fibrous base material layers are not shifted in different directions. It is possible to produce a printed wiring board by using, as a core substrate, a metal-clad laminate containing the insulating substrate. Also, it is possible to produce a semiconductor device by mounting a semiconductor element onto the printed wiring board. | 09-19-2013 |
Patent application number | Description | Published |
20150018794 | ABSORBENT ARTICLE - Provided is an absorbent article having a top sheet with an opening-formed area in which openings are formed, and non-opening-formed areas in which no openings are formed, said absorbent article being capable of preventing liquid from remaining on the surface of the opening-formed area of the top sheet. In the present invention, the top sheet is a resin sheet having an opening-formed area ( | 01-15-2015 |
20150018796 | ABSORBENT ARTICLE - Provided is an absorbent article which makes it easy to fold wing sections of the absorbent article so as to match the shape of the edges of the leg openings of underwear. The present invention is an absorbent article ( | 01-15-2015 |
20150057627 | ABSORBENT ARTICLE - The present invention addresses the problem of providing a novel absorbent article that prevents excessive compression of an absorbent body caused by deformation of the absorbent article, and rewetting associated with said compression. In order to solve such a problem, a sanitary napkin ( | 02-26-2015 |
20150065984 | ABSORBENT ARTICLE - Provided is an absorbent article capable of suppressing leakage in the widthwise direction from an absorbent article ( | 03-05-2015 |
20150080838 | ABSORBENT ARTICLE - Provided is an absorbent article that can prevent pulp fibers and a superabsorbent polymer (SAP) that constitute an absorbent body from leaking from openings, evening if a top sheet does not cover the side wall portions of the absorbent body at the openings. An absorbent article ( | 03-19-2015 |
20150238375 | NONWOVEN AND ABSORBENT ARTICLE - The purpose of the present invention is to provide a nonwoven for a top sheet of an absorbent article that is unlikely to stick after having absorbed menstrual blood, that is smooth and dry, and in which the absorbed menstrual blood is unlikely to diffuse on the nonwoven. This nonwoven has the following configuration. A nonwoven for a top sheet of an absorbent article, having a lengthwise direction and a crosswise direction, wherein the nonwoven has a plurality of ridge parts and a plurality of groove parts extending in the lengthwise direction and disposed in alternating fashion in the crosswise direction, the nonwoven being characterized in that the ridge parts and the groove parts have a plurality of through-holes, and the ridge parts have a region containing a blood lubricity-imparting agent that contains a predetermined blood lubricity-imparting agent. | 08-27-2015 |
Patent application number | Description | Published |
20140092384 | DIFFRACTION GRATING MANUFACTURING METHOD, SPECTROPHOTOMETER, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The present invention has been made in view of the above, and an object thereof is to provide a manufacturing technique capable of manufacturing a diffraction grating which is suitable for use in a spectrophotometer and has an apex angle of a convex portion of about 90° and can satisfy high diffraction efficiency and a low stray light amount. A method of manufacturing a diffraction grating, the method including: setting an exposure condition such that a sectional shape of a convex portion of a resist on a substrate, which has been formed by exposure, is an asymmetric triangle with respect to an opening portion shape of a mask having an opening portion with a periodic structure and an angle formed by a long side and a short side of the triangle is about 90°; and performing exposure. | 04-03-2014 |
20140302679 | PHASE SHIFT MASK, METHOD OF FORMING ASYMMETRIC PATTERN, METHOD OF MANUFACTURING DIFFRACTION GRATING, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A technique of forming an asymmetric pattern by using a phase shift mask, and further, techniques of manufacturing a diffraction grating and a semiconductor device, capable of improving accuracy of a product and capable of shortening manufacturing time. In a method of manufacturing a diffraction grating by using a phase shift mask (in which a light shield part and a light transmission part are periodically arranged), light emitted from an illumination light source is transmitted through the phase shift mask, and a photoresist on a surface of a Si wafer is exposed by providing interference between zero diffraction order light and positive first diffraction order light which are generated by the transmission through this phase shift mask onto the surface of the Si wafer, and a diffraction grating which has a blazed cross-sectional shape is formed on the Si wafer. | 10-09-2014 |
Patent application number | Description | Published |
20090142919 | Semiconductor device and manufacturing method of the same - In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP. | 06-04-2009 |
20110140275 | Semiconductor device and manufacturing method of the same - In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP. | 06-16-2011 |
20120270390 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP. | 10-25-2012 |
Patent application number | Description | Published |
20090050988 | MEMS APPARATUS AND METHOD OF MANUFACTURING THE SAME - A MEMS apparatus includes a MEMS unit formed on a semiconductor substrate and a cover provided with a pore and serving to seal the MEMS unit. The pore is sealed with a sealing material shaped in a sphere or a hemisphere. | 02-26-2009 |
20090206444 | INTEGRATED SEMICONDUCTOR DEVICE - An integrated semiconductor device includes a plurality of semiconductor elements having different integrated element circuits or different sizes; an insulating material arranged between the semiconductor elements; an organic insulating film arranged entirely on the semiconductor elements and the insulating material; a fine thin-layer wiring that arranged on the organic insulating film and connects the semiconductor elements; a first input/output electrode arranged on an area of the insulating material; and a first bump electrode formed on the first input/output electrode. | 08-20-2009 |
20130234308 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED DEVICE AND METHOD OF MANUFACTURING THE SAME - A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip. | 09-12-2013 |
20140091447 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire. | 04-03-2014 |
20150123275 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED DEVICE AND METHOD OF MANUFACTURING THE SAME - A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip. | 05-07-2015 |
Patent application number | Description | Published |
20150084208 | CONNECTION MEMBER, SEMICONDUCTOR DEVICE, AND STACKED STRUCTURE - A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane. | 03-26-2015 |
20150201488 | WIRING BOARD AND METHOD OF MANUFACTURING THE SAME - A wiring board of an embodiment includes a through via, a first insulating film disposed around the through via, a second insulating film disposed around the first insulating film, a third insulating film disposed around the second insulating film and a resin disposed around the third insulating film. The resin includes fillers. The second insulating film has a relative permittivity lower than a relative permittivity of the first insulating film. The third insulating film has a relative permittivity higher than a relative permittivity of the second insulating film. | 07-16-2015 |
20150279802 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a semiconductor chip, a cap disposed to face the semiconductor chip, and having a through-hole electrode arranged in a through hole, and a bump electrode provided between the semiconductor chip and the cap, wherein the bump electrode is in a protruding shape connecting the semiconductor chip and the through-hole electrode, and wherein at least a portion of the bump electrode is included in the through-hole electrode, and electrically connected thereto, so that the adhesive performance between the cap and the bump electrode can be increased. | 10-01-2015 |
20150348924 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device comprises an insulative resin, an interconnect, a plurality of semiconductor elements, a first conductive unit, a first connector, and a first metal layer. The insulative resin includes a first region and a second region. At least a portion of the interconnect is arranged with at least a portion of the first region in a first direction. The first conductive unit pierces the second region in the first direction. At least a portion of the first connector is arranged with at least a portion of the first conductive unit in the first direction. At least a portion of the first connector is arranged with at least a portion of the interconnect in a second direction intersecting the first direction. The first metal layer is provided between the first conductive unit and the first connector. The first metal layer contacts the insulative resin. | 12-03-2015 |
20150348937 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes an insulative resin, an interconnect, a plurality of semiconductor elements, and a first metal member. The insulative resin includes a first region and a second region. The interconnect is arranged with the first region in a first direction. The first direction intersects a direction from the first region toward the second region. The plurality of semiconductor elements is provided between the first region and the interconnect. At least one of the plurality of semiconductor elements is electrically connected to the interconnect. The first metal member includes a first through-portion and a first end portion. The first through-portion pierces the second region in the first direction. The first end portion is connected to the first through-portion. A width of the first end portion is wider than a width of the first through-portion in a second direction intersecting the first direction. | 12-03-2015 |
Patent application number | Description | Published |
20080318356 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a highly integrated, thin apparatus can be obtained, even if the apparatus contains MEMS devices and semiconductor devices. A semiconductor apparatus includes: a first chip comprising a MEMS device formed therein; a second chip comprising a semiconductor device formed therein; and an adhesive layer bonding a side face of the first chip to a side face of the second chip, and having a lower Young's modulus than the material of the first and second chips. | 12-25-2008 |
20090179317 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to restrict warpage at the time of resin cure and achieve a smaller thickness. A semiconductor device includes: a first chip including a MEMS device and a first pad formed on an upper face of the MEMS device, the first pad being electrically connected to the MEMS device; a second chip including a semiconductor device and a second pad formed on an upper face of the semiconductor device, the second pad being electrically connected to the semiconductor device; and an adhesive portion having a stacked structure, and bonding a side face of the first chip and a side face of the second chip, the stacked structure including a first adhesive film formed by adding a first material constant modifier to a first resin, and a second adhesive film formed by adding a second material constant modifier to a second resin. | 07-16-2009 |
20150021748 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a substrate, a high-frequency integrated circuit being provided on the substrate, a cap, and a sealing wall provided between the substrate and the cap. The cap includes a first conductive layer, a second conductive layer, an insulating layer provided between the first conductive layer and the second conductive layer, and a conductive via provided in the insulating layer. The conductive via connects the first conductive layer and the second conductive layer. The first conductive layer or the second conductive layer is connected to a ground potential. The sealing wall surrounds the high-frequency integrated circuit. | 01-22-2015 |
20150022416 | ANTENNA DEVICE - An antenna device of the present embodiment includes: a first conductive layer connected to a ground potential, a semiconductor device provided above the first conductive layer, a second conductive layer provided above the semiconductor device, a first via connecting the second conductive layer and the first conductive layer, a third conductive layer provided above the second conductive layer, a second via passing through the first opening, and an antenna provided above the third conductive layer. A dielectric is provided between the second conductive layer and the semiconductor device, between the third conductive layer and the second conductive layer, and between the antenna and the third conductive layer. The second conductive layer includes a first opening. The second via connects the third conductive layer and the first conductive layer. | 01-22-2015 |