Patent application number | Description | Published |
20080258205 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - An erase current of a non-volatile semiconductor memory device is decreased. A memory cell of the non-volatile semiconductor memory device comprises a source region and a drain region formed in a semiconductor substrate. Over a portion of the semiconductor substrate between the source region and the drain region, a select gate electrode is formed via a gate dielectric film. On a side wall of the select gate electrode, a memory gate electrode is formed via a bottom silicon oxide film and a charge-trapping silicon oxynitride film. In the memory cell configured as above, erase operation is performed as follows. By applying a positive voltage to the memory gate electrode, holes are injected from the memory gate electrode into the silicon oxynitride film to decrease a threshold voltage in a program state to a certain level. Thereafter, hot holes generated by a band-to-band tunneling phenomenon are injected into the silicon oxynitride film and the erase operation is completed. | 10-23-2008 |
20080265286 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×10 | 10-30-2008 |
20080290401 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICES WITH CHARGE INJECTION CORNER - An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved. | 11-27-2008 |
20090014775 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. | 01-15-2009 |
20090050955 | NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced. | 02-26-2009 |
20090050956 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In a memory cell including an nMIS for memory formed on the sides of an nMIS for select and an nMIS for select via dielectric films and a charge storage layer, the thickness of a gate dielectric under the gate longitudinal direction end of a select gate electrode is formed thicker than that of the gate dielectric under the gate longitudinal direction center and the thickness of the lower layer dielectric film that is positioned between the select gate electrode and the charge storage layer and is nearest to a semiconductor substrate is formed 1.5 times or below of the thickness of the lower layer dielectric film positioned between the semiconductor substrate and the charge storage layer. | 02-26-2009 |
20090122609 | SEMICONDUCTOR DEVICE - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section. | 05-14-2009 |
20090152619 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down. | 06-18-2009 |
20100038700 | Semiconductor Device - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section. | 02-18-2010 |
20100135080 | FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other. | 06-03-2010 |
20100203697 | INTEGRATED SEMICONDUCTOR NONVOLATILE STORAGE DEVICE - An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. | 08-12-2010 |
20100232231 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. | 09-16-2010 |
20110181987 | MAGNETIC RECORDING/REPRODUCTION HEAD - Provided is a differential type reproduction head which can obtain a preferable bit error rate without causing a baseline shift even when two magnetoresistive elements have different maximum resistance change amounts. The differential type reproduction head has a layered structure formed by a first magnetoresistive element having a first free layer, a differential gap layer, and a second magnetoresistive element having a second free layer. When DR | 07-28-2011 |
20120026798 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. | 02-02-2012 |
20120086070 | FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other. | 04-12-2012 |
20130028058 | ENERGY-ASSISTED MAGNETIC RECORDING HEAD AND MAGNETIC RECORDING DEVICE - In a case in which a microwave-assisted magnetic recording system is applied to a shingled write system for recording with high density, the width of a high-frequency generation element is narrower than a track width of main pole, and both steep parts of magnetic field gradients | 01-31-2013 |
20130065368 | NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING EMBEDDED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SIDEWALL GATE - A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation. | 03-14-2013 |
20130140622 | NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced. | 06-06-2013 |
20130228845 | FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other. | 09-05-2013 |
20140322874 | NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced. | 10-30-2014 |