Patent application number | Description | Published |
20090281908 | System for the Creation, Production, and Distribution of Music - The present invention provides a system for purchasing music in integrated songs or divided into manipulatable components and then create new works with these components in unique productions and then release and distribute such music in either integrated or non integrated form stored with information that tracks the relative royalty characteristics of the stems/components of the song for later accounting and distribution of royalties to the owners of the song/song components/stems based on the purchase reproduction and resale of the components/stems/songs. | 11-12-2009 |
20100147139 | ELECTRONIC MUSICAL PERFORMANCE INSTRUMENT WITH GREATER AND DEEPER FLEXIBILITY - An electronic musical performance instrument that provides a user with a wide array of creative choices of operating systems, sound synthesis applications, user interfaces (including those emulating the interface of a conventional musical instrument and electronic control interfaces), supporting infrastructure components such as MIDI cards, sound cards, storage devices thus providing the performance artist with greater and deeper creative flexibility. | 06-17-2010 |
20110069049 | ORGANIC LED CONTROL SURFACE DISPLAY CIRCUITRY - An embodiment of a display apparatus includes a display panel having at least one segment line, at least one common line, and at least one display element coupled between the at least one segment line and the at least one common line. The display apparatus further includes a first segment driver circuit having at least one first segment driver coupled to a first end of the at least one segment line, and a second segment driver circuit having at least one second segment driver coupled to a second end of the at least one segment line. The display apparatus further includes a first common driver circuit having at least one first common driver coupled to a first end of the at least one common line, and a second common driver circuit having at least one second common driver coupled to a second end of the at least one common line. | 03-24-2011 |
Patent application number | Description | Published |
20080219067 | INDIVIDUAL I/O MODULATION IN MEMORY DEVICES - A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster. | 09-11-2008 |
20090086565 | System and Method for Processing Signals in High Speed DRAM - A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at least a portion of the first duration of clock cycles. In one embodiment, the first duration of the activate signal is at least four clock cycles, and the bank address signal is at least one clock cycle. A memory device having a row decoder and an active driver is also provided. | 04-02-2009 |
20090273989 | Synchronous Command Base Write Recovery Time Auto Precharge Control - Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal. | 11-05-2009 |
20100110813 | PRECHARGE CONTROL CIRCUITS AND METHODS FOR MEMORY HAVING BUFFERED WRITE COMMANDS - Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed. | 05-06-2010 |
20100250874 | APPARATUS AND METHOD FOR BUFFERED WRITE COMMANDS IN A MEMORY - Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command. | 09-30-2010 |
20110026345 | PRECHARGE CONTROL CIRCUITS AND METHODS FOR MEMORY HAVING BUFFERED WRITE COMMANDS - Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed. | 02-03-2011 |
20110194367 | SYSTEMS, MEMORIES, AND METHODS FOR REFRESHING MEMORY ARRAYS - Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to the digit line of at least one section of the memory cell array and coupled to the digit line of the replacement element. Memories include control logic configured to selectively refresh the replacement element at an occurrence when a non-neighboring section of the memory cell array relative to the replacement element is refreshed. Other memories, systems, and methods are provided. | 08-11-2011 |
20110205831 | SYSTEM AND METHOD FOR PROCESSING SIGNALS IN HIGH SPEED DRAM - A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal. An activate command executes on every first duration of clock cycles, and the bank address signal is high for at least a portion of the first duration of clock cycles. In one embodiment, the first duration of the activate signal is at least four clock cycles, and the bank address signal is at least one clock cycle. A memory device having a row decoder and an active driver is also provided. | 08-25-2011 |
20110216621 | Synchronous Command-Based Write Recovery Time Auto Precharge Control - Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal. | 09-08-2011 |
20120263001 | SYSTEMS, MEMORIES, AND METHODS FOR REFRESHING MEMORY ARRAYS - Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to a digit line of at least one section of the memory cell array and coupled to the digit line of the replacement element. Memories include control logic configured to selectively refresh the replacement element at an occurrence when a non-neighboring section of the memory cell array relative to the replacement element is refreshed. Other memories, systems, and methods are provided. | 10-18-2012 |
20120324179 | APPARATUS AND METHOD FOR BUFFERED WRITE COMMANDS IN A MEMORY - Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command. | 12-20-2012 |
20130242685 | SYSTEM AND METHOD FOR PROCESSING SIGNALS IN HIGH SPEED DRAM - The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle. | 09-19-2013 |
Patent application number | Description | Published |
20090050101 | PISTON AND INTERNAL COMBUSTION ENGINE THEREWITH AND METHOD OF CONSTRUCTING THE PISTON - A piston and internal combustion engine therewith constructed in accordance with the present invention has a piston body with an upper crown having a substantially cylindrical outer surface depending from a top surface along a central axis. At least one annular ring groove extends radially into the outer surface to provide a top land extending from the ring groove to the top surface. A plurality of waves are formed circumferentially about the top land. Each of the waves has a valley extending radially into the outer surface of the top land and extending from the top surface to the ring groove. The waves traverse from the top surface to the ring groove and are configured in substantially non-overlapping relation with one another and in a predetermined orientation relative to at least one of a fuel spray stream, a pin bore axis or a thrust axis of the piston. | 02-26-2009 |
20090260350 | ENHANCED AFTERTREATMENT APPARATUS REGENERATION USING SPATIALLY CONTROLLED HYDROGEN-RICH GAS - Regeneration system in which a hydrogen-rich gas from an onboard reformer flows into an aftertreatment unit in a direction opposite to the flow of engine exhaust to regenerate the unit. The aftertreatment unit is segmented with independent regeneration capability for each segment. Regeneration is performed with hydrogen-rich gas produced by an onboard reformer. A hydrogen-rich gas switchbox is used to direct the flow of the reformate to the segment of the aftertreatment unit that is undergoing regeneration. | 10-22-2009 |
20100266461 | Method For Reducing Pressure Drop Through Filters, And Filter Exhibiting Reduced Pressure Drop - Methods for generating and applying coatings to filters with porous material in order to reduce large pressure drop increases as material accumulates in a filter, as well as the filter exhibiting reduced and/or more uniform pressure drop. The filter can be a diesel particulate trap for removing particulate matter such as soot from the exhaust of a diesel engine. Porous material such as ash is loaded on the surface of the substrate or filter walls, such as by coating, depositing, distributing or layering the porous material along the channel walls of the filter in an amount effective for minimizing or preventing depth filtration during use of the filter. Efficient filtration at acceptable flow rates is achieved. | 10-21-2010 |
20130269528 | Method For Reducing Pressure Drop Through Filters, And Filter Exhibiting Reduced Pressure Drop - Methods for generating and applying coatings to filters with porous material in order to reduce large pressure drop increases as material accumulates in a filter, as well as the filter exhibiting reduced and/or more uniform pressure drop. The filter can be a diesel particulate trap for removing particulate matter such as soot from the exhaust of a diesel engine. Porous material such as ash is loaded on the surface of the substrate or filter walls, such as by coating, depositing, distributing or layering the porous material along the channel walls of the filter in an amount effective for minimizing or preventing depth filtration during use of the filter. Efficient filtration at acceptable flow rates is achieved. | 10-17-2013 |
20140116028 | Particulate Filter Control System And Method - A system and method for controlling the operation of a particulate filter is disclosed. The objective of this control system is to manipulate the properties and spatial distribution of contaminant material accumulated in filters to reduce filter pressure drop and associated deleterious impacts of the contaminant material on filter performance. | 05-01-2014 |
Patent application number | Description | Published |
20080287285 | RHODIUM CONTAINING CATALYSTS - The present invention addresses at least four different aspects relating to catalyst structure, methods of making those catalysts and methods of using those catalysts for making alkenyl alkanoates. Separately or together in combination, the various aspects of the invention are directed at improving the production of alkenyl alkanoates and VA in particular, including reduction of by-products and improved production efficiency. A first aspect of the present invention pertains to a unique palladium/gold catalyst or pre-catalyst (optionally calcined) that includes rhodium or another metal. A second aspect pertains to a palladium/gold catalyst or pre-catalyst that is based on a layered support material where one layer of the support material is substantially free of catalytic components. A third aspect pertains to a palladium/gold catalyst or pre-catalyst on a zirconia containing support material. A fourth aspect pertains to a palladium/gold catalyst or pre-catalyst that is produced from substantially chloride free catalytic components. | 11-20-2008 |
20080287289 | HALIDE FREE PRECURORS FOR CATALYSTS - The present invention addresses at least four different aspects relating to catalyst structure, methods of making those catalysts and methods of using those catalysts for making alkenyl alkanoates. Separately or together in combination, the various aspects of the invention are directed at improving the production of alkenyl alkanoates and VA in particular, including reduction of by-products and improved production efficiency. A first aspect of the present invention pertains to a unique palladium/gold catalyst or pre-catalyst (optionally calcined) that includes rhodium or another metal. A second aspect pertains to a palladium/gold catalyst or pre-catalyst that is based on a layered support material where one layer of the support material is substantially free of catalytic components. A third aspect pertains to a palladium/gold catalyst or pre-catalyst on a zirconia containing support material. A fourth aspect pertains to a palladium/gold catalyst or pre-catalyst that is produced from substantially chloride free catalytic components. | 11-20-2008 |
20080287290 | LAYERED SUPPORT MATERIAL FOR CATALYSTS - The present invention addresses at least four different aspects relating to catalyst structure, methods of making those catalysts and methods of using those catalysts for making alkenyl alkanoates. Separately or together in combination, the various aspects of the invention are directed at improving the production of alkenyl alkanoates and VA in particular, including reduction of by-products and improved production efficiency. A first aspect of the present invention pertains to a unique palladium/gold catalyst or pre-catalyst (optionally calcined) that includes rhodium or another metal. A second aspect pertains to a palladium/gold catalyst or pre-catalyst that is based on a layered support material where one layer of the support material is substantially free of catalytic components. A third aspect pertains to a palladium/gold catalyst or pre-catalyst on a zirconia containing support material. A fourth aspect pertains to a palladium/gold catalyst or pre-catalyst that is produced from substantially chloride free catalytic components. | 11-20-2008 |
20100144539 | HIGH PRESSURE PARALLEL FIXED BED REACTOR AND METHOD - The present invention discloses an apparatus and method for rapid analysis of members of a combinatorial library. The apparatus includes a plurality of reactor vessels for containing individual library members, a fluid handling system that apportions a test fluid about equally between each of the vessels and a housing for enclosing the reactor vessels, the housing defining a pressure chamber, wherein the housing is configured to sustain a pressure substantially above atmospheric pressure. This allows for simultaneous screening of library members at high pressure by providing a small pressure differential on reactor components. The disclosed apparatus is especially useful for screening library members based on their ability to catalyze the conversion of fluid reactants. | 06-10-2010 |
20140038855 | High Pressure Parallel Fixed Bed Reactor and Method - Apparatus and methods provide rapid analysis of members of a combinatorial library. The apparatus includes a plurality of reactor vessels for containing individual library members, a fluid handling system that apportions a test fluid about equally between each of the vessels, and a housing for enclosing the reactor vessels. The housing defines a pressure chamber configured to sustain a pressure substantially above atmospheric pressure. This allows for simultaneous screening of library members at high pressure by providing a small pressure differential on reactor components. The apparatus is used for screening library members based on their ability to catalyze the conversion of fluid reactants. | 02-06-2014 |
Patent application number | Description | Published |
20140245076 | SYSTEM AND METHOD FOR PRESERVING CRITICAL DEBUG DATA IN A PORTABLE COMPUTING DEVICE - One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers. | 08-28-2014 |
20140359374 | SYSTEM AND METHOD FOR MANAGING TRACE DATA IN A PORTABLE COMPUTING DEVICE - Systems, methods, and computer programs for managing trace data in a portable computing device are disclosed. One system includes a system-on-chip and a trace parser. The system-on-chip may have a plurality of trace sources for originating corresponding trace data and a trace system configured to receive and dump the trace data from one of the trace sources to a plurality of trace sinks. The trace parser is configured to reconstruct the trace data dumped to the plurality of trace sinks. | 12-04-2014 |
20150033082 | Method and Apparatus for Multi-chip Reduced Pin Cross Triggering To Enhance Debug Experience - Embodiments include apparatuses, systems, and methods for reduced pin cross triggering to enhance a debug experience. A time-division packetizing (TDP) technique may be employed to facilitate communication of triggers between integrated circuits (ICs) connected in series forming a TDP communication ring. The ICs on the TDP communication ring may each include a cross trigger interconnect structure for interpreting between trigger signals and hardware core instructions. The serial TDP communication across the ICs on the TDP communication ring allows the ICs to be connected in a manner that each cross trigger interconnect structure on each IC may function as if it were part of a single cross trigger interconnect structure across all of the ICs on the TDP communication ring. The individual ICs may operate asynchronously and a trigger clock may be passed along with other trigger data to implement the debugging techniques uniformly on each IC. | 01-29-2015 |
20150046617 | SYSTEM AND METHOD FOR SCALABLE TRACE UNIT TIMESTAMPING - An integrated circuit includes a trace subsystem that provides timestamps for events occurring in a trace source that does not natively support time stamping trace data. A timestamp inserter is coupled to such a trace source. The timestamp inserter generates a modified trace data stream by arranging a reference or references with the trace information from the trace source on a trace bus. A trace destination receives the modified trace data stream including the reference(s). In some embodiments, a timestamp inserter receives a timestamp request and stores a reference in a buffer. Upon later receipt of trace information associated with the request, the timestamp inserter inserts the reference, a current reference and the received trace information into the trace data stream. | 02-12-2015 |