Patent application number | Description | Published |
20100304236 | CATALYSTS AND METHODS INCLUDING STEAM REFORMING - The present invention generally relates to catalyst compositions comprising aluminates, such as nickel aluminates, and related methods. In some embodiments, the catalyst composition may be advantageously modified, for example, by the addition of one or more metal additives to further enhance catalyst performance. Such modifications can provide a more effective catalyst and can reduce the level of coking during catalytic processes. Some embodiments of the invention may provide effective catalyst compositions for steam reforming. In some cases, the catalyst composition may be utilized under relatively mild reaction conditions. | 12-02-2010 |
20120295421 | LOW TEMPERATURE SELECTIVE EPITAXY OF SILICON GERMANIUM ALLOYS EMPLOYING CYCLIC DEPOSIT AND ETCH - Cyclic deposit and etch (CDE) selective epitaxial growth employs an etch chemistry employing a combination of hydrogen chloride and a germanium-containing gas to provide selective deposition of a silicon germanium alloy at temperatures lower than 625° C. High strain epitaxial silicon germanium alloys having a germanium concentration greater than 35 atomic percent in a temperature range between 400° C. and 550° C. A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium-containing precursor gas is employed to deposit the silicon germanium alloy with thickness uniformity and at a high deposition rate during each deposition step in this temperature range. Presence of the germanium-containing gas in the etch chemistry enhances the etch rate of the deposited silicon germanium alloy material during the etch step. | 11-22-2012 |
20130040438 | EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 - A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH | 02-14-2013 |
20130040440 | EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 - A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH | 02-14-2013 |
20130161693 | THIN HETEREOSTRUCTURE CHANNEL DEVICE - A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure. | 06-27-2013 |
20130161694 | THIN HETEREOSTRUCTURE CHANNEL DEVICE - A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure. | 06-27-2013 |
20140045324 | LOW TEMPERATURE EPITAXY OF A SEMICONDUCTOR ALLOY INCLUDING SILICON AND GERMANIUM EMPLOYING A HIGH ORDER SILANE PRECURSOR - A high order silane having a formula of Si | 02-13-2014 |
20140167162 | FINFET WITH MERGE-FREE FINS - A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions. | 06-19-2014 |
20140170825 | FINFET WITH MERGE-FREE FINS - A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions. | 06-19-2014 |
20140264596 | PARTIALLY ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTORS - A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates. | 09-18-2014 |
20140264603 | PARTIALLY ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTORS - A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates. | 09-18-2014 |
20140312433 | CONTACT STRUCTURE EMPLOYING A SELF-ALIGNED GATE CAP - After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion. | 10-23-2014 |
20140315379 | CONTACT STRUCTURE EMPLOYING A SELF-ALIGNED GATE CAP - After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion. | 10-23-2014 |
20140374839 | SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN FORMED ON BULK AND GATE CHANNEL FORMED ON OXIDE LAYER - A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins. | 12-25-2014 |
20140377917 | SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN FORMED ON BULK AND GATE CHANNEL FORMED ON OXIDE LAYER - A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins. | 12-25-2014 |
20150041908 | METHOD OF MANUFACTURING A FinFET DEVICE USING A SACRIFICIAL EPITAXY REGION FOR IMPROVED FIN MERGE AND FinFET DEVICE FORMED BY SAME - A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors. | 02-12-2015 |
20150048429 | SIDEWALL IMAGE TRANSFER WITH A SPIN-ON HARDMASK - Semiconductor devices and sidewall image transfer methods with a spin on hardmask. Methods for forming fins include forming a trench through a stack of layers that includes a top and bottom insulator layer, and a layer to be patterned on a substrate; isotropically etching the top and bottom insulator layers; forming a hardmask material in the trench to the level of the bottom insulator layer; isotropically etching the top insulator layer; and etching the bottom insulator layer and the layer to be patterned down to the substrate to form fins from the layer to be patterned. | 02-19-2015 |
20150048430 | SIDEWALL IMAGE TRANSFER WITH A SPIN-ON HARDMASK - Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure. | 02-19-2015 |
20150054077 | FINFET FORMED OVER DIELECTRIC - A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material. | 02-26-2015 |
20150054121 | FINFET FORMED OVER DIELECTRIC - A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material. | 02-26-2015 |
20150061015 | NON-MERGED EPITAXIALLY GROWN MOSFET DEVICES - Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins. | 03-05-2015 |
20150061077 | TRENCH SIDEWALL PROTECTION FOR SELECTIVE EPITAXIAL SEMICONDUCTOR MATERIAL FORMATION - A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures. | 03-05-2015 |
20150064884 | TRENCH SIDEWALL PROTECTION FOR SELECTIVE EPITAXIAL SEMICONDUCTOR MATERIAL FORMATION - A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures. | 03-05-2015 |
20150069327 | FIN FIELD-EFFECT TRANSISTORS WITH SUPERLATTICE CHANNELS - FinFET structures may be formed including superlattice fins. The structure may include a superlattice fin of alternating layers of silicon-germanium with a germanium concentration of approximately 10% to 80% and a second semiconductor material. In some embodiments, the second semiconductor material may include either silicon or carbon-doped silicon. Where the second semiconductor material is carbon-doped silicon, the carbon concentration may range from approximately 0.2% to approximately 4%. The superlattice fin may have a height ranging from approximately 5 nm to approximately 100 nm and include between 5 and 30 alternating layers of silicon-germanium and the second semiconductor material. A gate may be formed over the superlattice fin and a source/drain region may be formed over an end of the superlattice fin. | 03-12-2015 |
20150108572 | Electrically Isolated SiGe FIN Formation By Local Oxidation - A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein. | 04-23-2015 |
20150140762 | FINFET WITH MERGE-FREE FINS - A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions. | 05-21-2015 |
Patent application number | Description | Published |
20130325756 | GRAPH-BASED FRAMEWORK FOR MULTI-TASK MULTI-VIEW LEARNING - A system and method a Multi-Task Multi-View (M | 12-05-2013 |
20130338808 | Method and Apparatus for Hierarchical Wafer Quality Predictive Modeling - An apparatus for performing enhanced wafer quality prediction in a semiconductor manufacturing process includes memory, for storing historical data relating to the semiconductor manufacturing process, and at least one processor in operative communication with the memory. The processor is operative: to obtain data including tensor format wafer processing conditions, historical wafer quality measurements and/or prior knowledge relating to at least one of the semiconductor manufacturing process and wafer quality; to build a hierarchical prediction model including at least the tensor format wafer processing conditions; and to predict wafer quality for a newly fabricated wafer based at least on the hierarchical prediction model and corresponding tensor format wafer processing conditions. | 12-19-2013 |
20130339919 | Method and Apparatus for Hierarchical Wafer Quality Predictive Modeling - A method for performing enhanced wafer quality prediction in a semiconductor manufacturing process includes the steps of: obtaining data including at least one of tensor format wafer processing conditions, historical wafer quality measurements and prior knowledge relating to at least one of the semiconductor manufacturing process and wafer quality; building a hierarchical prediction model including at least the tensor format wafer processing conditions; and predicting wafer quality for a newly fabricated wafer based at least on the hierarchical prediction model and corresponding tensor format wafer processing conditions. | 12-19-2013 |
20140031968 | Run-to-Run Control Utilizing Virtual Metrology in Semiconductor Manufacturing - A method for run-to-run control and sampling optimization in a semiconductor manufacturing process includes the steps of: determining a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process; determining a predicted process output and corresponding prediction error associated with a virtual metrology for the current processing run; and controlling at least one parameter corresponding to a subsequent processing run as a function of the metrology error and the prediction error. | 01-30-2014 |
20140031969 | Run-to-Run Control Utilizing Virtual Metrology in Semiconductor Manufacturing - An apparatus for performing run-to-run control and sampling optimization in a semiconductor manufacturing process includes at least one control module. The control module is operative: to determine a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process; to determine a predicted process output and corresponding prediction error associated with a virtual metrology for the current processing run; and to control at least one parameter corresponding to a subsequent processing run as a function of the metrology error and the prediction error. | 01-30-2014 |
20140107824 | Method and System for Wafer Quality Predictive Modeling based on Multi-Source Information with Heterogeneous Relatedness - The present invention generally relates to the monitoring and controlling of a semiconductor manufacturing environment and, more particularly, to methods and systems for virtual meteorology (VM) applications based on data from multiple tools having heterogeneous relatedness. The methods and systems leverage the natural relationship of the multiple tools and take advantage of the relationship embedded in process variables to improve the prediction performance of the VM predictive wafer quality modeling. The prediction results of the methods and systems can be used as a substitute for or in conjunction with actual metrology samples in order to monitor and control a semiconductor manufacturing environment, and thus reduce delays and costs associated with obtaining actual physical measurements. | 04-17-2014 |
20140107828 | Method and System for Wafer Quality Predictive Modeling based on Multi-Source Information with Heterogeneous Relatedness - The present invention generally relates to the monitoring and controlling of a semiconductor manufacturing environment and, more particularly, to methods and systems for virtual meteorology (VM) applications based on data from multiple tools having heterogeneous relatedness. The methods and systems leverage the natural relationship of the multiple tools and take advantage of the relationship embedded in process variables to improve the prediction performance of the VM predictive wafer quality modeling. The prediction results of the methods and systems can be used as a substitute for or in conjunction with actual metrology samples in order to monitor and control a semiconductor manufacturing environment, and thus reduce delays and costs associated with obtaining actual physical measurements. | 04-17-2014 |
Patent application number | Description | Published |
20110320387 | Graph-based transfer learning - Transfer learning is the task of leveraging the information from labeled examples in some domains to predict the labels for examples in another domain. It finds abundant practical applications, such as sentiment prediction, image classification and network intrusion detection. A graph-based transfer learning framework propagates label information from a source domain to a target domain via the example-feature-example tripartite graph, and puts more emphasis on the labeled examples from the target domain via the example-example bipartite graph. An iterative algorithm renders the framework scalable to large-scale applications. The framework propagates the label information to both features irrelevant to the source domain and unlabeled examples in the target domain via common features in a principled way. | 12-29-2011 |
20130018827 | SYSTEM AND METHOD FOR AUTOMATED LABELING OF TEXT DOCUMENTS USING ONTOLOGIESAANM He; JingruiAACI OssiningAAST NYAACO USAAGP He; Jingrui Ossining NY USAANM Lawrence; Richard D.AACI RidgefieldAAST CTAACO USAAGP Lawrence; Richard D. Ridgefield CT USAANM Melville; PremAACI White PlainsAAST NYAACO USAAGP Melville; Prem White Plains NY USAANM Sindhwani; VikasAACI HawthorneAAST NYAACO USAAGP Sindhwani; Vikas Hawthorne NY USAANM Chenthamarakshan; Vijil E.AACI OssiningAAST NYAACO USAAGP Chenthamarakshan; Vijil E. Ossining NY US - A first mapping function automatically maps a plurality of documents each with a concept of ontology to create a documents-to-ontology distribution. An ontology-to-class distribution that maps concepts in the ontology to class labels, respectively, is received, and a classifier is generated that labels a selected document with an associated class identified based on the documents-to-ontology distribution and the ontology-to-class distribution. | 01-17-2013 |
20130018828 | SYSTEM AND METHOD FOR AUTOMATED LABELING OF TEXT DOCUMENTS USING ONTOLOGIES - A first mapping function automatically maps a plurality of documents each with a concept of ontology to create a documents-to-ontology distribution. An ontology-to-class distribution that maps concepts in the ontology to class labels, respectively, is received, and a classifier is generated that labels a selected document with an associated class identified based on the documents-to-ontology distribution and the ontology-to-class distribution. | 01-17-2013 |
20130046768 | FINDING A TOP-K DIVERSIFIED RANKING LIST ON GRAPHS - A method, system and computer program product for finding a diversified ranking list for a given query. In one embodiment, a multitude of date items responsive to the query are identified, a marginal score is established for each data item; and a set, or ranking list, of the data items is formed based on these scores. This ranking list is formed by forming an initial set, and one or more data items are added to the ranking list based on the marginal scores of the data items. In one embodiment, each of the data items has a measured relevance and a measured diversity value, and the marginal scores for the data items are based on the measured relevance and the measured diversity values of the data items. | 02-21-2013 |
20130046769 | MEASURING THE GOODNESS OF A TOP-K DIVERSIFIED RANKING LIST - A method, system and computer program product for measuring a relevance and diversity of a ranking list to a given query. The ranking list is comprised of a set of data items responsive to the query. In one embodiment, the method comprises calculating a measured relevance of the set of data items to the query using a defined relevance measuring procedure, and determining a measured diversity value for the ranking list using a defined diversity measuring procedure. The measured relevance and the measured diversity value are combined to obtain a measure of the combined relevance and diversity of the ranking list. The measured relevance of the set of data items may be based on the individual relevance of each of the data items to the query, and the diversity value may be based on the similarities of the data items to each other. | 02-21-2013 |
Patent application number | Description | Published |
20130244421 | METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE - Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes the steps of forming a trench/via in a layer of insulating material, forming a copper-based seed layer above the layer of insulating material and in the trench/via, performing a heating process on the copper-based seed layer to increase an amount of the copper-based seed layer positioned proximate a bottom of the trench/via, performing an etching process on said copper-based seed layer and performing an electroless copper deposition process to fill the trench/via with a copper-based material. | 09-19-2013 |
20130309863 | METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES BY FORMING A COPPER-BASED SEED LAYER HAVING AN AS-DEPOSITED THICKNESS PROFILE AND THEREAFTER PERFORMING AN ETCHING PROCESS AND ELECTROLESS COPPER DEPOSITION - Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating material, performing a deposition process to form an as-deposited copper-based seed layer above the layer of insulating material in the trench/via, wherein the copper-based seed layer has a first portion that is positioned above a bottom of the trench/via that is thicker than second portions of the copper seed layer that are positioned above sidewalls of the trench/via, performing an etching process on the as-deposited copper-based seed layer to substantially remove portions of the second portions of the as-deposited copper-based seed layer and performing an electroless deposition process to fill the trench/via with a copper-based material. | 11-21-2013 |
20140057435 | METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE - Disclosed herein are various methods of forming a metal cap layer on copper-based conductive structures on integrated circuit devices, and integrated circuit devices having such a structure. In one example, the method includes the steps of forming a conductive feature comprised of copper in a layer of insulating material, performing a metal removal process to remove a portion of the conductive feature and thereby define a recess above a residual portion of the copper feature, and performing a selective deposition process to form a cap layer comprised of cobalt, manganese, CoWP or NiWP within the recess. | 02-27-2014 |
20140145332 | METHODS OF FORMING GRAPHENE LINERS AND/OR CAP LAYERS ON COPPER-BASED CONDUCTIVE STRUCTURES - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a graphene liner layer in at least the trench/via, forming a copper-based seed layer on the graphene liner layer, depositing a bulk copper-based material on the copper-based seed layer so as to overfill the trench/via, and performing at least one chemical mechanical polishing process to remove at least excess amounts of the bulk copper-based material and the copper-based seed layer positioned outside of the trench/via to thereby define a copper-based conductive structure with a graphene liner layer positioned between the copper-based conductive structure and the layer of insulating material. | 05-29-2014 |
20140217588 | METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FOR CONDUCTIVE COPPER STRUCTURES AND THE RESULTING DEVICE - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material. | 08-07-2014 |
20140252616 | ELECTROLESS FILL OF TRENCH IN SEMICONDUCTOR STRUCTURE - A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench. | 09-11-2014 |
20140353802 | METHODS FOR INTEGRATION OF PORE STUFFING MATERIAL - A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided. | 12-04-2014 |
20140353805 | METHODS OF SEMICONDUCTOR CONTAMINANT REMOVAL USING SUPERCRITICAL FLUID - A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided. | 12-04-2014 |
20140353835 | METHODS OF SELF-FORMING BARRIER INTEGRATION WITH PORE STUFFED ULK MATERIAL - A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench. | 12-04-2014 |
20140361435 | METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FOR CONDUCTIVE COPPER STRUCTURES AND THE RESULTING DEVICE - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material. | 12-11-2014 |
20150087149 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING IMPROVED MASKS - Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask. | 03-26-2015 |
Patent application number | Description | Published |
20100010237 | FUSED THIOPHENES, METHODS FOR MAKING FUSED THIOPHENES, AND USES THEREOF - Described herein are compositions including heterocyclic organic compounds such as fused thiophene compounds, methods for making them, and uses thereof | 01-14-2010 |
20100305288 | Fused Thiophenes, Articles, and Methods Thereof - Fused thiophene (FT) compounds, FT polymers, FT containing articles, and methods for making and using the FT compounds and polymers thereof of the formulas, as defined herein. | 12-02-2010 |
20110040042 | FUSED THIOPHENES, METHODS FOR MAKING FUSED THIOPHENES, AND USES THEREOF - Described herein are compositions including heterocyclic organic compounds such as fused thiophene compounds, methods for making them, and uses thereof. | 02-17-2011 |
20110082278 | FUSED THIOPHENES, METHODS FOR MAKING FUSED THIOPHENES, AND USES THEREOF - Described herein are compositions including heterocyclic organic compounds such as fused thiophene compounds, methods for making them, and uses thereof. | 04-07-2011 |
20110098478 | FUSED THIOPHENES AND METHODS FOR MAKING AND USING SAME - Disclosed are compounds having one of the following formulae (11), (12), wherein X is an aromatic nucleophilic substitution leaving group; R | 04-28-2011 |
20110281121 | Surface Treatment and Article - Surfaces having hydrophobic/oleophobic properties and methods of making them. The surfaces disclosed may be used, for example, in touch screen applications or other applications that involve contact with human skin. | 11-17-2011 |
20110281393 | Method of Making an Organic Semiconductor Device - A method of making an organic semiconductor device that comprises providing a surface comprising surface hydroxyl groups; applying an amine to the surface to form a first coated surface; applying a silane compound to the first coated surface to form a second coated surface; exposing the second coated surface to conditions sufficient to chemically react the silane compound with the hydroxyl groups to form a hydrophobic surface; and applying an organic semiconducting material to the hydrophobic surface. | 11-17-2011 |
20110288306 | METHODS OF MAKING FUSED THIOPHENES - β″-di-R-substituted fused thiophene (DCXFT4) compounds, and a method for making a compound of the formula (V): | 11-24-2011 |
20110291054 | POLYMERIC FUSED THIOPHENE SEMICONDUCTOR FORMULATION - A formulation including:
| 12-01-2011 |
20110291077 | Enhanced Semiconductor Devices Employing Photoactive Organic Materials And Methods Of Manufacturing Same - Methods and apparatus provide for a transistor, including: a semiconductor layer including molecules, protons, and/or ions, etc. diffused therein from a photoactive material; a channel disposed on or in the semiconductor layer; a source disposed on or in the semiconductor layer; a drain disposed on or in the semiconductor layer; and a gate electrically coupled to the semiconductor layer. | 12-01-2011 |
20120022116 | COMPOSITIONS AND METHODS FOR THE TREATMENT OF PATHOLOGICAL CONDITION(S) RELATED TO GPR35 AND/OR GPR35-HERG COMPLEX - Disclosed are compositions and methods for the prevention and/or treatment of diseases which are pathophysiologically related to GPR35, and/or GPR35-hERG signaling complex. For example, disclosed are compounds for preventing and/or treating diseases which are pathophysiologically related to GPR35 in a subject. The compounds having a formula (I), (II) or (III): | 01-26-2012 |
20120035375 | DI-TIN FUSED THIOPHENE COMPOUNDS AND POLYMERS AND METHODS OF MAKING - Di-tin fused thiophene (FT) compounds, FT polymers, such as of the formula -{-(FTx)-(Ar) | 02-09-2012 |
20120220713 | SOLVENT MIXTURE FOR MOLECULAR WEIGHT CONTROL - A method of making a polymer, including: heating, for a sufficient time and temperature, to polymerize a homogenous mixture including of at least one polymerizable monomer, and a solvent mixture comprised of at least a first liquid and a second liquid, the first liquid being a stronger solvent for the product polymer than the weaker second liquid, and the polymer product precipitates from the homogenous mixture during the heating, as defined herein. Also disclosed are semiconducting articles and printable inks prepared with the resulting narrow polydispersity polymers, as defined herein. | 08-30-2012 |
20120220748 | FIVE-RING FUSED HETEROAROMATIC COMPOUNDS AND CONJUGATED POLYMERS THEREOF - Compounds having a core comprised of an aromatic ring and at least two annulated beta-substituted fused thiophene ring systems of the general formula: | 08-30-2012 |
20120280368 | LAMINATED STRUCTURE FOR SEMICONDUCTOR DEVICES - Articles are described utilizing laminated glass substrates, for example, ion-exchanged glass substrates, with flexible glass or polymers and with semiconductor devices which may be sensitive to alkali migration are described along with methods for making the articles. | 11-08-2012 |
20120280373 | ACTIVE ELECTRONICS ON STRENGTHENED GLASS WITH ALKALI BARRIER - Articles are described utilizing strengthened glass substrates, for example, ion-exchanged glass substrates, with oxide or nitride containing alkali barrier layers and with semiconductor devices which may be sensitive to alkali migration are described along with methods for making the articles. | 11-08-2012 |
20120295965 | FUSED THIOPHENES AS DUAL INHIBITORS OF EGFR/VEGFR AND THEIR USE IN THE TREATMENT OF CANCER - Disclosed are compositions and methods related to identification of modulators of EGFR and VEGFR. | 11-22-2012 |
20120329865 | MOLECULES RELATED hERG ION CHANNELS AND THE USE THEREOF - Disclosed are compounds having structural formula (I, II) or a pharmaceutically acceptable sale, solvate, clathrate, or prodrug thereof, wherein R | 12-27-2012 |
20130085256 | FUSED THIOPHENES, METHODS OF MAKING FUSED THIOPHENES, AND USES THEREOF - Described herein are compositions including heterocyclic organic compounds based on fused thiophene compounds, polymers based on fused thiophene compounds, and methods for making the monomers and polymer along with uses in thin film-based and other devices. | 04-04-2013 |
20130109821 | CONJUGATED FUSED THIOPHENES, METHODS OF MAKING CONJUGATED FUSED THIOPHENES, AND USES THEREOF | 05-02-2013 |
20130114219 | OPTO-ELECTRONIC FRONTPLANE SUBSTRATE - Frontplane articles are described utilizing laminated glass substrates, for example, ion-exchanged glass substrates, with flexible glass and with opto-electronic devices which may be sensitive to alkali migration are described along with methods for making the articles. | 05-09-2013 |
20130140540 | ORGANIC THIN FILM TRANSISTOR WITH ION EXCHANGED GLASS SUBSTRATE - Articles utilizing strengthened glass substrates, for example, ion-exchanged glass substrates, in combination with organic molecules or polymers are described along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors. | 06-06-2013 |
20130178599 | FIVE-RING FUSED HETEROAROMATIC COMPOUNDS AND CONJUGATED POLYMERS THEREOF - Compounds having a core comprised of an aromatic ring and at least two annulated beta-substituted fused thiophene ring systems of the general formula: | 07-11-2013 |
20130270494 | MERCAPTOFUNCTIONAL HIGH MUBETA EO CHROMOPHORES AND HIGH TG, LOW OPTICAL LOSS, COVALENTLY BONDED, HIGH MUBETA EO CHROMOPHORE CONTAINING POLYMERS AND METHODS OF SYNTHESIZING EO MATERIALS - The present invention relates generally to mercaptofunctional high μβ EO chromophores and EO polymers, and particularly to mercaptofunctional high μβ EO chromophores and EO polymers useful for making electro-optical devices and systems. Mercaptofunctional high μβ EO chromophores are covalently bonded to poly(imido sulfide) polymers producing high Tg, low optical loss, covalently bonded, high μβ EO chromophore containing polymers. Methods of synthesizing these EO materials using mild polymerization conditions are also described. | 10-17-2013 |
20130281707 | FUSED THIOPHENES AND METHODS FOR MAKING AND USING SAME - Disclosed are compounds having one of the following formulae: | 10-24-2013 |
20140246631 | MERCAPTOFUNCTIONAL HIGH MUBETA EO CHROMOPHORES AND HIGH TG, LOW OPTICAL LOSS, COVALENTLY BONDED, HIGH MUBETA EO CHROMOPHORE CONTAINING POLYMERS AND METHODS OF SYNTHESIZING EO MATERIALS - The present invention relates generally to mercaptofunctional high μβ EO chromophores and EO polymers, and particularly to mercaptofunctional high μβ EO chromophores and EO polymers useful for making electro-optical devices and systems. Mercaptofunctional high μβ EO chromophores are covalently bonded to poly(imido sulfide) polymers producing high Tg, low optical loss, covalently bonded, high μβ EO chromophore containing polymers. Methods of synthesizing these EO materials using mild polymerization conditions are also described. | 09-04-2014 |
20150045560 | NOVEL FUSED NAPHTHALENE CYCLOHETERO RING COMPOUNDS, AND METHODS AND USES THEREOF - Described herein are heterocyclic organic compounds of following formulae: More specifically, described herein are fused heterocyclic naphthalene compounds, polymers based on fused heterocyclic naphthalene compounds, methods for making these compounds, and uses thereof. The compounds described have improved polymerization and stability properties that allow for improved material processibility for use as organic semiconductors (OSCs). | 02-12-2015 |
20150057420 | BORON ESTER FUSED THIOPHENE MONOMERS - A compound of formula (I), formula (II), or a combination thereof, and salts thereof is described. | 02-26-2015 |
20150065722 | FUSED THIOPHENE DITIN MONOMERS - The disclosure relates to thiophene-based ditin compounds and methods of making and using such compounds. The disclosed compounds are novel structures having organotin groups on a conjugated aryl group spaced from and adjacent to a fused thiophene moiety. The formation of trialkyl tin groups spaced away from the fused thiophene moieties is advantageous in that it allows for novel polymerization via Stille coupling. | 03-05-2015 |
Patent application number | Description | Published |
20130253808 | Estimating Incident Duration - A method, an apparatus and an article of manufacture for incident duration prediction. The method includes obtaining incident data for at least one traffic-related incident in a selected geographic area, obtaining traffic data for the selected geographic area, spatially and temporally associating the at least one traffic-related incident with the traffic data to generate incident duration data for the at least one traffic-related incident, and predicting incident duration of at least one additional traffic-related incident based on the incident duration data for the at least one traffic-related incident. | 09-26-2013 |
20140164389 | MINING TRAJECTORY FOR SPATIAL TEMPORAL ANALYTICS - Embodiments relate to generating a trajectory heat map at an aggregated level using computed transit points is provided. An aspect includes generating, by a processing device, a trajectory database from time-stamped global positioning system (GPS) sample points. According to exemplary embodiments, transit points are computed for each trajectory in the trajectory database. A temporal transit graph is constructed from the transit points. The transit graph of embodiments captures the shortest paths among these transit points. The transit graph is then indexed and stored in a spatial-temporal database for online analytic processing. | 06-12-2014 |
20140164390 | MINING TRAJECTORY FOR SPATIAL TEMPORAL ANALYTICS - Embodiments relate to generating a trajectory heat map at an aggregated level using computed transit points is provided. An aspect includes generating, by a processing device, a trajectory database from time-stamped global positioning system (GPS) sample points. According to exemplary embodiments, transit points are computed for each trajectory in the trajectory database. A temporal transit graph is constructed from the transit points. The transit graph of embodiments captures the shortest paths among these transit points. The transit graph is then indexed and stored in a spatial-temporal database for online analytic processing. | 06-12-2014 |
20140200827 | RAILWAY TRACK GEOMETRY DEFECT MODELING FOR PREDICTING DETERIORATION, DERAILMENT RISK, AND OPTIMAL REPAIR - Geo-defect repair modeling is provided. A method includes logically dividing a railroad network according to spatial and temporal dimensions with respect to historical data collected. The spatial dimensions include line segments of a specified length and the temporal dimensions include inspection run data for inspections performed for each of the line segments over a period of time. The method also includes creating a track deterioration model from the historical data, identifying geo-defects occurring at each inspection run from the track deterioration model, calculating a track deterioration condition from the track deterioration model by analyzing quantified changes in the geo-defects measured at each inspection run, and calculating a derailment risk based on track conditions determined from the inspection run data and the track deterioration condition. The method further includes determining a repair decision for each of the geo-defects based on the derailment risk and costs associated with previous comparable repairs. | 07-17-2014 |
20140200830 | RAILWAY TRACK GEOMETRY DEFECT MODELING FOR PREDICTING DETERIORATION, DERAILMENT RISK, AND OPTIMAL REPAIR - Geo-defect repair modeling is provided. A method includes logically dividing a railroad network according to spatial and temporal dimensions with respect to historical data collected. The spatial dimensions include line segments of a specified length and the temporal dimensions include inspection run data for inspections performed for each of the line segments over a period of time. The method also includes creating a track deterioration model from the historical data, identifying geo-defects occurring at each inspection run from the track deterioration model, calculating a track deterioration condition from the track deterioration model by analyzing quantified changes in the geo-defects measured at each inspection run, and calculating a derailment risk based on track conditions determined from the inspection run data and the track deterioration condition. The method further includes determining a repair decision for each of the geo-defects based on the derailment risk and costs associated with previous comparable repairs. | 07-17-2014 |
Patent application number | Description | Published |
20140200869 | LARGE-SCALE MULTI-DETECTOR PREDICTIVE MODELING - Predicting operational changes in a multi-detector environment includes generating, via a computer processing device, a factor matrix for each univariate time series data in a set of sparse time series data collected from data sources, identifying a subset of the time series data as a feature selection based on application of a loss function, and generating a predictive model from the subset of the time series data. | 07-17-2014 |
20140200870 | LARGE-SCALE MULTI-DETECTOR PREDICTIVE MODELING - Predicting operational changes in a multi-detector environment includes generating, via a computer processing device, a factor matrix for each univariate time series data in a set of sparse time series data collected from data sources, identifying a subset of the time series data as a feature selection based on application of a loss function, and generating a predictive model from the subset of the time series data. | 07-17-2014 |
20140200872 | ONLINE LEARNING USING INFORMATION FUSION FOR EQUIPMENT PREDICTIVE MAINTENANCE IN RAILWAY OPERATIONS - An aspect of an online learning system includes collecting data, via a computer processing device, from a plurality of data sources including multiple disparate detectors, the data including at least one of historical alarm data, failures, maintenance records, and environment observations. The data is stored in tables each corresponding to a subject of measurement. The online learning system also includes identifying common fields shared across the tables, merging at least a portion of the data across the tables having the common fields, and creating an integrated data model based on results of the merging. | 07-17-2014 |
20140200873 | ONLINE LEARNING USING INFORMATION FUSION FOR EQUIPMENT PREDICTIVE MAINTENANCE IN RAILWAY OPERATIONS - An aspect of an online learning system includes collecting data, via a computer processing device, from a plurality of data sources including multiple disparate detectors, the data including at least one of historical alarm data, failures, maintenance records, and environment observations. The data is stored in tables each corresponding to a subject of measurement. The online learning system also includes identifying common fields shared across the tables, merging at least a portion of the data across the tables having the common fields, and creating an integrated data model based on results of the merging. | 07-17-2014 |
20150073686 | TRAFFIC CONTROL AGENCY DEPLOYMENT AND SIGNAL OPTIMIZATION FOR EVENT PLANNING - Embodiments relate to traffic control resource planning. An aspect includes receiving information about available routes in a transportation network and receiving an estimate of a traffic demand in the transportation network. Traffic control planning is performed and it may include: simulating a traffic flow based on the available routes and the traffic demand; applying a model that varies traffic control agent (TCA) placement and traffic signal settings in the transportation network to minimize a cost associated with the traffic flow, the cost including a TCA deployment cost and a traffic delay cost; and outputting a traffic control plan based on the applying, the traffic control plan including a TCA placement and traffic signal setting plan. | 03-12-2015 |
20150073687 | TRAFFIC CONTROL AGENCY DEPLOYMENT AND SIGNAL OPTIMIZATION FOR EVENT PLANNING - Embodiments relate to traffic control resource planning. An aspect includes receiving information about available routes in a transportation network and receiving an estimate of a traffic demand in the transportation network. Traffic control planning is performed and it may include: simulating a traffic flow based on the available routes and the traffic demand; applying a model that varies traffic control agent (TCA) placement and traffic signal settings in the transportation network to minimize a cost associated with the traffic flow, the cost including a TCA deployment cost and a traffic delay cost; and outputting a traffic control plan based on the applying, the traffic control plan including a TCA placement and traffic signal setting plan. | 03-12-2015 |
20150073688 | Traffic Impact Prediction for Multiple Event Planning - Embodiments relate to traffic impact prediction in a transportation network. Link level background traffic demand in a transportation network may be estimated based on information about available routes, and based on expected background traffic volumes between origins and destinations. A background traffic flow model that optimizes a background flow of the expected background traffic volumes among the available routes to minimize a sum of background congestion costs, background path entropy, and errors between an observed background traffic flow and the optimized background flow may be applied. Alternative routes may be identified based on the available routes and event based control plans. Expected additional event based traffic volumes may be received. A link level total traffic demand in the transportation network may be estimated based on the expected additional event based traffic volumes, the identified alternative routes, and the estimated background traffic demand. | 03-12-2015 |
20150073689 | Traffic Impact Prediction for Multiple Event Planning - Embodiments relate to traffic impact prediction in a transportation network. Link level background traffic demand in a transportation network may be estimated based on information about available routes, and based on expected background traffic volumes between origins and destinations. A background traffic flow model that optimizes a background flow of the expected background traffic volumes among the available routes to minimize a sum of background congestion costs, background path entropy, and errors between an observed background traffic flow and the optimized background flow may be applied. Alternative routes may be identified based on the available routes and event based control plans. Expected additional event based traffic volumes may be received. A link level total traffic demand in the transportation network may be estimated based on the expected additional event based traffic volumes, the identified alternative routes, and the estimated background traffic demand. | 03-12-2015 |
Patent application number | Description | Published |
20100050607 | System and method for controlling exhaust stream temperature - Systems and methods are provided for controlling an exhaust stream temperature at a point along an exhaust system. The exhaust system can include an oxidation catalyst, a particulate filter having an outlet, and a fuel injector for injecting fuel into an exhaust stream at a location upstream from the outlet. An adaptive control can be provided to model a portion of the exhaust system. A fuel injection flow rate at which fuel is injected into the exhaust stream by the fuel injector can be calculated based on the adaptive control model. An operation of the fuel injector can be controlled based on the calculated fuel injection flow rate, to control the exhaust stream temperature at point along the exhaust system. A condition of the exhaust stream can also monitored and an error in the adaptive control model can be determined based on the monitored condition. The adaptive control model can also be changed to reduce the error. | 03-04-2010 |
20100126144 | Systems And Methods For Estimating Particulate Load In A Particulate Filter - A method for regenerating a particulate filter may comprise determining a temperature, a flow rate, and a total pressure drop of an exhaust gas flowing through a particulate filter, and determining a corrected soot layer permeability. The method may further comprise calculating an estimated soot load of the particulate filter based on the total pressure drop and the corrected soot layer permeability, and causing regeneration of the particulate filter when the estimated soot load is greater than or equal to a threshold value. | 05-27-2010 |
20100126145 | Methods For Estimating Particulate Load In A Particulate Filter, And Related Systems - A method for regenerating a particulate filter may comprise calculating a first estimated soot load of a particulate filter based on a pressure drop of an exhaust gas flowing through the particulate filter, and calculating a second estimated soot load of the particulate filter based on a mass balance of soot in the particulate filter. The method may further comprise calculating a hybrid estimated soot load based on the first estimated soot load and the second estimated soot load, wherein calculating the hybrid estimated soot load comprises applying at least one gate so as to weight a relative contribution of each of the first estimated soot load and the second estimated soot load to the hybrid estimated soot load, and causing regeneration of the particulate filter when the hybrid estimated soot load is greater than or equal to a threshold value. | 05-27-2010 |
20100300070 | Systems And Methods For Controlling Temperature And Total Hydrocarbon Slip - Systems and methods for controlling temperature and total hydrocarbon slip in an exhaust system are provided. Control systems can comprise an oxidation catalyst, a particulate filter, a fuel injector, and a processor for controlling a fuel injection based on an oxidation catalyst model. Example system includes a virtual sensor comprising a controller for calculating and providing the total hydrocarbon slip to subsystems for after-treatment management based on modeling the oxidation catalyst. Example methods for controlling the temperature and the total hydrocarbon slip in an exhaust system include the steps of providing an oxidation catalyst model, monitoring a condition of the exhaust system, calculating a hydrocarbon fuel injection flow rate and controlling a fuel injection. The example methods further include the steps of determining an error in the oxidation catalyst model based on the monitored condition and changing the oxidation catalyst model to reduce the error. | 12-02-2010 |
20110120088 | Mass Based Methods And Systems For Estimating Soot Load - Mass based methods and systems for estimating soot load in a filter of an after-treatment system for exhaust stream are provided. The after-treatment system can comprise a sensor, a filter, and a processor configured to estimate soot load in the filter based on a mass based multi-layer model. An example system includes a virtual sensor comprising an estimator for providing information corresponding to a filter outlet NO | 05-26-2011 |
20110209460 | Systems And Methods For Determining A Particulate Load In A Particulate Filter - A method for regenerating a particulate filter may comprise calculating a soot layer state correction factor based on a rate of regeneration and a rate of particulate loading in the particulate filter and calculating an estimated soot load in the particulate filter based on a pressure drop of an exhaust gas flowing through the particulate filter and the calculated soot layer state correction factor. The method for regenerating the particulate filter may further comprise causing regeneration of the particulate filter when the estimated soot load is greater than or equal to a threshold value. | 09-01-2011 |
20120230881 | HONEYCOMB FILTERS FOR REDUCING NOx AND PARTICULATE MATTER IN DIESEL ENGINE EXHAUST - Particulate filters for reducing NO | 09-13-2012 |
20130045139 | Method To Enhance The Ash Storage Capacity Of A Particulate Filter - A method of treating a particulate filter includes introducing a work fluid, such as water, into one or more channels of the filter and then removing the work fluid in a vaporized state. The channels contain an amount of ash and the density of the ash is greater subsequent to the removal of the work fluid than prior to the introduction of the work fluid. | 02-21-2013 |
20130192205 | SYSTEMS AND METHODS FOR CONTROLLING TEMPERATURE AND TOTAL HYDROCARBON SLIP - Systems and methods for controlling temperature and total hydrocarbon slip in an exhaust system are provided. Control systems can comprise an oxidation catalyst, a particulate filter, a fuel injector, and a processor for controlling a fuel injection based on an oxidation catalyst model. Example system includes a virtual sensor comprising a controller for calculating and providing the total hydrocarbon slip to subsystems for after-treatment management based on modeling the oxidation catalyst. Example methods for controlling the temperature and the total hydrocarbon slip in an exhaust system include the steps of providing an oxidation catalyst model, monitoring a condition of the exhaust system, calculating a hydrocarbon fuel injection flow rate and controlling a fuel injection. The example methods further include the steps of determining an error in the oxidation catalyst model based on the monitored condition and changing the oxidation catalyst model to reduce the error. | 08-01-2013 |
20140208946 | PARTIAL WALL-FLOW FILTER AND METHOD - A partial wall-flow filter has an inlet end, an outlet end, and a plurality of parallel channels disposed and configured to flow fluid from the inlet end to the outlet end. The channels are defined by a plurality of porous walls. A first portion of the channels have a first hydraulic diameter Dh1, a second portion of the channels have a second hydraulic diameter Dh2 smaller than the first hydraulic diameter Dh1, and the ratio of Dh1:Dh2 is in the range of 1.1 to 1.6. At least a portion of channels having hydraulic diameter Dh1 are plugged at the outlet end, and channels having hydraulic diameter Dh2 are flow-through channels. | 07-31-2014 |
20140238242 | CERAMIC PARTIAL WALL-FLOW FILTER WITH LOW DEEP BED - A partial wall-flow filter, having a honeycomb structure including an inlet end, an outlet end, and parallel channels disposed and configured to flow fluid from the inlet end to the outlet end. The channels are defined by a plurality of intersecting porous walls. The partial wall-flow filter has a filtration region of channels plugged at the outlet end and a bypass region of unplugged channels. An N/S ratio of the filter material is less than or equal to about 0.5, less than or equal to about 0.3, less than or equal to about 0.1, or even 0, where N is a pressure drop difference induced by deep bed soot and S is a pressure drop change from 0 grams per liter (g/l) to about 5 g/l for a conditioned curve induced by cake bed soot, where N and S are measured on a full wall-flow filter of the filter material. | 08-28-2014 |
Patent application number | Description | Published |
20120246638 | FORECASTING BASED SERVICE ASSIGNMENT IN CLOUD COMPUTING - A mechanism is provided for reassigning virtual machines to resources in a computing environment. Monitoring data is collected about virtual machine request history and resource usage in a form of time series for measured indicators. Forecasted time series are computed for the measured indicators over a time window by utilizing time series forecasting. A new assignment is computed by executing a snapshot based assignment algorithm on the forecasted time series. The new assignment is used for reassignment of virtual machines on the resources in the computing environment. | 09-27-2012 |
20130155879 | QUASI-DYNAMIC SPECTRUM ACCESS FOR INTERNET OF THINGS (IOT) APPLICATIONS - Spectrum access for Internet of things (IOT) applications including receiving information about expected use by a primary user of a spectrum band in a radio frequency spectrum. The spectrum band is classified into at least two working modes based on the expected use. The spectrum band is sensed to determine a current access pattern of the primary user. Based on the classifying and the sensing, one of the working modes is selected as a current working mode of the primary user. Transmissions are scheduled on the spectrum band using a current schedule that is responsive to the current working mode of the primary user. If the current working mode of the primary user changes, the sensing, selecting, scheduling, and determining whether the current working mode has changed are re-performed. Otherwise, the transmission scheduling and determining if the current working mode has changed are re-performed. | 06-20-2013 |
20130190026 | ENHANCED RESOURCE MANAGEMENT FOR A NETWORK SYSTEM - According to exemplary embodiments, a method for resource management of network systems includes sampling channel states of a first set of channels from at least one base station associated with a radio network controller providing an application and estimating channel states of a second set of channels from the at least one base station, wherein the estimated channel states are based on previously sampled channel states and currently sampled channel states. The method further includes adapting at least one runtime parameter of the application based on the sampled channel states of the first set of channels and the estimated channel states of the second set of channels. | 07-25-2013 |
20140201753 | SCHEDULING MAPREDUCE JOBS IN A CLUSTER OF DYNAMICALLY AVAILABLE SERVERS - There is provided a method, a system and a computer program product for improving performance and fairness in sharing a cluster of dynamically available computing resources among multiple jobs. The system collects at least one parameter associated with availability of a plurality of computing resources. The system calculates, based on the collected parameter, an effective processing time each computing resource can provide to each job. The system allocates, based on the calculated effective processing time, the computing resources to the multiple jobs, whereby the multiple jobs are completed at a same time or an approximate time. | 07-17-2014 |
20150029870 | BOUNDED-BUDGET MONITOR DEPLOYMENT IN MONITORING NETWORKS VIA END-TO-END PROBES - The present disclosure relates generally to mechanisms for bounded-budget monitor deployment in monitoring networks via end-to-end probes. In various embodiments, methodologies may be provided that automatically perform bounded-budget monitor deployment in monitoring networks via end-to-end probes. | 01-29-2015 |