Patent application number | Description | Published |
20090047801 | INTERFACING TWO INSULATION PARTS IN HIGH VOLTAGE ENVIRONMENT - Methods of interfacing parts in a high voltage environment and related structures are disclosed. A method comprises: providing an insulation medium between a first part and a second part in a high voltage environment; and interfacing the first part and the second part by compressing the first part and the second part against the insulation medium. | 02-19-2009 |
20090057573 | TECHNIQUES FOR TERMINAL INSULATION IN AN ION IMPLANTER - Techniques for terminal insulation for an ion implanter are disclosed. In one particular exemplary embodiment, the techniques may be realized as an ion implanter comprising a terminal structure defining a terminal cavity. The ion implanter may also comprise a grounded enclosure defining a grounded cavity and the terminal structure may be at least partially disposed within the grounded cavity. The ion implanter may further comprise an intermediate terminal structure disposed proximate an exterior portion of the terminal structure and at least partially disposed within the grounded cavity. | 03-05-2009 |
20090072163 | TECHNIQUES FOR CONTROLLING A CHARGED PARTICLE BEAM - Techniques for controlling a charged particle beam are disclosed. In one particular exemplary embodiment, the techniques may be realized as a charged particle acceleration/deceleration system. The charged particle acceleration/deceleration system may comprise an acceleration column. The acceleration column may comprise a plurality of electrodes having apertures through which a charged particle beam may pass. The charged particle acceleration/deceleration system may also comprise a plurality of resistors electrically coupled to the plurality of electrodes. The charged particle acceleration/deceleration system may further comprise a plurality of switches electrically coupled to the plurality of electrodes and the plurality of resistors, each of the plurality of switches may be configured to be selectively switched respectively in a plurality of operation modes. | 03-19-2009 |
20090078554 | TECHNIQUES FOR MAKING HIGH VOLTAGE CONNECTIONS - Techniques for making high voltage connections are disclosed. In one particular exemplary embodiment, the techniques may be realized as an electrical switch. The electrical switch may comprise a component extending from a first electrical contact to a second electrical contact. The component may also comprise a non-conductive section and a conductive section. In a first mode of operation, at least a portion of the non-conductive section may be positioned between the two electrical contacts to insulate the two electrical contacts. In a second mode of operation, the conductive section may be positioned between the two electrical contacts to connect the two electrical contacts. | 03-26-2009 |
20090085504 | TECHNIQUES FOR CONTROLLING A CHARGED PARTICLE BEAM - Techniques for controlling a charged particle beam are disclosed. In one particular exemplary embodiment, the techniques may be realized as a charged particle acceleration/deceleration system. The charged particle acceleration/deceleration system may comprise an accelerator column, which may comprise a plurality of electrodes. The plurality of electrodes may have apertures through which a charged particle beam may pass. The charged particle acceleration/deceleration system may also comprise a voltage grading system. The voltage grading system may comprise a first fluid reservoir and a first fluid circuit. The first fluid circuit may have conductive connectors connecting to at least one of the plurality of electrodes. The voltage grading system may further comprise fluid in the first fluid circuit. The fluid may have an electrical resistance. | 04-02-2009 |
20110094798 | INTERFACING TWO INSULATION PARTS IN HIGH VOLTAGE ENVIRONMENT - Methods of interfacing parts in a high voltage environment and related structures are disclosed. A method comprises: providing a first part and a second part; and interfacing the first part and the second part to create a first substantially zero electrical field area at a first outer extent of an interface between the first and second parts and a reduced electrical field area in a different portion of the interface. | 04-28-2011 |
20110094862 | TECHNIQUES FOR MAKING HIGH VOLTAGE CONNECTIONS - Techniques for making high voltage connections are disclosed. In one particular exemplary embodiment, the techniques may be realized as an electrical switch. The electrical switch may comprise a component extending from a first electrical contact to a second electrical contact. The component may also comprise a non-conductive section and a conductive section. In a first mode of operation, at least a portion of the non-conductive section may be positioned between the two electrical contacts to insulate the two electrical contacts. In a second mode of operation, the conductive section may be positioned between the two electrical contacts to connect the two electrical contacts. | 04-28-2011 |
20140127394 | Reducing Glitching In An Ion Implanter - Methods of reducing glitch rates within an ion implanter are described. In one embodiment, a plasma-assisted conditioning is performed, wherein the bias voltage to the extraction electrodes is modified so as to inhibit the formation of an ion beam. The power supplied to the plasma generator in the ion source is increased, thereby creating a high density plasma, which is not extracted by the extraction electrodes. This plasma extends from the arc chamber through the extraction aperture. Energetic ions then condition the extraction electrodes. In another embodiment, a plasma-assisted cleaning is performed. In this mode, the extraction voltage applied to the arc chamber body is modulated between two voltages so as to clean both the extraction electrodes and the faceplate of the arc chamber body. | 05-08-2014 |
20150055261 | SYSTEM AND METHOD OF PROVIDING ISOLATED POWER TO GATE DRIVING CIRCUITS IN SOLID STATE FAULT CURRENT LIMITERS - A system and method for providing isolated power to the gate driving circuits used in solid state switching devices is disclosed. Rather than using expensive isolated AC/DC power supplies, an isolation transformer is used to provide isolated AC voltage. In one embodiment, the primary winding of the isolation transformer is disposed across an independent AC source. In another embodiment, the primary winding of the isolation transformer is disposed across two phases of the AC power line. Isolated AC voltage is then generated across the secondary winding of the isolation transformer. This isolated AC voltage is then used by a non-isolated DC power supply, which generates the power for the gate driving circuit. | 02-26-2015 |
Patent application number | Description | Published |
20090044179 | MEDIA FOR PERFORMING PARALLEL PROCESSING OF DISTRIBUTED ARRAYS - One or more computer-readable media store executable instructions that, when executed by processing logic, perform parallel processing. The media store one or more instructions for initiating a single programming language, and identifying, via the single programming language, one or more data distribution schemes for executing a program. The media also store one or more instructions for transforming, via the single programming language, the program into a parallel program with an optimum data distribution scheme selected from the one or more identified data distribution schemes, and allocating the parallel program to two or more labs for parallel execution. The media further store one or more instructions for receiving one or more results associated with the parallel execution of the parallel program from the two or more labs, and providing the one or more results to the program. | 02-12-2009 |
20090044180 | DEVICE FOR PERFORMING PARALLEL PROCESSING OF DISTRIBUTED ARRAYS - A device for performing parallel processing includes a processor to initiate a single programming language, and identify, via the single programming language, one or more data distribution schemes for executing a program. The processor also transforms, via the single programming language, the program into a parallel program with an optimum data distribution scheme selected from the one or more identified data distribution schemes, and allocates the parallel program to two or more labs for parallel execution. The processor further receives one or more results associated with the parallel execution of the parallel program from the two or more labs, and provides the one or more results to the program. | 02-12-2009 |
20090044196 | METHOD OF USING PARALLEL PROCESSING CONSTRUCTS - A computing device-implemented method includes receiving a program, analyzing and transforming the program, determining an inner context and an outer context of the program based on the analysis of the program, and allocating one or more portions of the inner context of the program to two or more labs for parallel execution. The method also includes receiving one or more results associated with the parallel execution of the one or more portions from the two or more labs, and providing the one or more results to the outer context of the program. | 02-12-2009 |
20090044197 | DEVICE FOR USING PARALLEL PROCESSING CONSTRUCTS - A device, for performing parallel processing, includes a processor to receive one or more portions of an inner context of a program created for a technical computing environment, and allocate one or more portions of the inner context of the program to two or more labs for parallel execution. The processor is also configured to receive one or more results associated with the parallel execution of the one or more portions from the two or more labs, and provide the one or more results to an outer context of the program. | 02-12-2009 |
20090049435 | PARALLEL PROCESSING OF DISTRIBUTED ARRAYS - A computing device-implemented method includes initiating a single programming language, and identifying, via the single programming language, one or more data distribution schemes for executing a program. The method also includes transforming, via the single programming language, the program into a parallel program with an optimum data distribution scheme selected from the one or more identified data distribution schemes, and allocating the parallel program to two or more labs for parallel execution. The method further includes receiving one or more results associated with the parallel execution of the parallel program from the two or more labs, and providing the one or more results to the program. | 02-19-2009 |
20090132867 | MEDIA FOR USING PARALLEL PROCESSING CONSTRUCTS - One or more computer-readable media store executable instructions that, when executed by processing logic, perform parallel processing. The media store one or more instructions for receiving one or more portions of an inner context of a program created for a technical computing environment, allocating one or more portions of the inner context of the program to two or more labs for parallel execution, receiving one or more results associated with the parallel execution of the one or more portions from the two or more labs, and providing the one or more results to an outer context of the program. | 05-21-2009 |
20120284726 | PERFORMING PARALLEL PROCESSING OF DISTRIBUTED ARRAYS - One or more computer-readable media store executable instructions that, when executed by processing logic, perform parallel processing. The media store one or more instructions for initiating a single programming language, and identifying, via the single programming language, one or more data distribution schemes for executing a program. The media also store one or more instructions for transforming, via the single programming language, the program into a parallel program with an optimum data distribution scheme selected from the one or more identified data distribution schemes, and allocating the parallel program to two or more labs for parallel execution. The media further store one or more instructions for receiving one or more results associated with the parallel execution of the parallel program from the two or more labs, and providing the one or more results to the program. | 11-08-2012 |
20120317165 | USING PARALLEL PROCESSING CONSTRUCTS AND DYNAMICALLY ALLOCATING PROGRAM PORTIONS - A computing device-implemented method includes receiving a program, analyzing and transforming the program, determining an inner context and an outer context of the program based on the analysis of the program, and allocating one or more portions of the inner context of the program to two or more labs for parallel execution. The method also includes receiving one or more results associated with the parallel execution of the one or more portions from the two or more labs, and providing the one or more results to the outer context of the program. | 12-13-2012 |