Patent application number | Description | Published |
20140167614 | ARC CHAMBER WITH MULTIPLE CATHODES FOR AN ION SOURCE - An apparatus for extending the useful life of an ion source, comprising an arc chamber containing a plurality of cathodes to be used sequentially and a plurality of repellers to protect cathodes when not in use. The arc chamber includes an arc chamber housing defining a reaction cavity, gas injection openings, a plurality of cathodes, and at least one repeller element. A method for extending the useful life of an ion source includes providing power to a first cathode of an arc chamber in an ion source, operating the first cathode, detecting a failure or degradation in performance of the first cathode, energizing a second cathode, and continuing operation of the arc chamber with the second cathode. | 06-19-2014 |
20140210057 | METHOD OF APPLYING PHOTORESIST TO A SEMICONDUCTOR SUBSTRATE - A method comprises dispensing a first solvent on a semiconductor substrate; dispensing a first layer of a high-viscosity polymer on the first solvent; dispensing a second solvent on the first layer of high-viscosity polymer; and spinning the semiconductor substrate after dispensing the second solvent, so as to spread the high-viscosity polymer to a periphery of the semiconductor substrate. | 07-31-2014 |
20140267692 | AUTOMATED WAFER INSPECTION - In semiconductor fabrication processes, one or more wafers are often exposed to processes such as chemical vapor deposition to form semiconductor components thereupon. Often, some of the wafers exhibit flaws due to contamination or processing errors occurring before, during, or after component formation. Inspection of the wafers is often performed by direct visual inspection of humans, which is prone to errors due to flaws that are too small to view directly; to particles naturally arising in the human eye; and to fatigue caused by inspection of large numbers of wafers. Presented herein are inspection techniques involving positioning the wafer in a dark chamber exposing the surface of the wafer to a light source at a first angle, and capturing with a camera an image of the light source reflected from the surface of the wafer at a second angle. Wafers identified as exhibiting flaws are removed from the wafer set. | 09-18-2014 |
20140273459 | Systems and Methods for a Narrow Band High Transmittance Interference Filter - The present disclosure provides an interference filter, a lithography system incorporating an interference filter, and a method of fabricating an interference filter. The interference filter includes a transparent substrate having a front surface and a back surface, a plurality of alternating material layers formed over the front surface of the transparent substrate that form a bandpass filter, and an anti-reflective structure formed over the back surface of the transparent substrate. The alternating material layers alternate between a relatively high refractive index material and a relatively low refractive index material. | 09-18-2014 |
20140340665 | ULTRAVIOLET LIGHT EMITTING DIODE ARRAY LIGHT SOURCE FOR PHOTOLITHOGRAPHY AND METHOD - A light source includes a plurality of ultraviolet (UV) light emitting diodes (LEDs) and an LED phase shift controller coupled to the plurality of UV LEDs adapted to control the phase shift of each UV LED in the plurality of UV LEDs. The plurality of UV LEDs forms a UV LED array. An ultraviolet lithography system can include a light source as described above. The system can further include a mirror assembly in a light path of the light source, the mirror assembly having a polarization mirror with an interference coating. A method provides a light source for an ultraviolet lithography system including the element of providing an plurality of UV LEDs that emit UV light and the element of controlling a phase shift of the plurality of UV LEDs with an LED phase shift controller coupled to each UV LED or arrays of the UV LEDs in the plurality of UV LEDs. | 11-20-2014 |
20150038056 | TEMPERATURE MODIFICATION FOR CHEMICAL MECHANICAL POLISHING - Among other things, one or more systems and techniques for increasing temperature for chemical mechanical polishing (CMP) are provided. For example, a liquid heater component is configured to supply heated liquid to a polishing pad upon which a semiconductor wafer is to be polished, resulting in a heated polishing pad having a heated polishing pad temperature. The increased temperature of the heated polishing pad increases oxidation of the semiconductor wafer, which improves a CMP removal rate of material from the semiconductor wafer due to a decreased oxidation timespan and a stabilization timespan for reaching a stable CMP removal rate during CMP. In this way, the semiconductor wafer is polished utilizing the heated polishing pad, such as by a tungsten CMP process. | 02-05-2015 |
20150079806 | Photoresist Coating Scheme - A method includes rotating a wafer at a first speed for a first time duration. The wafer is rotated at a second speed that is lower than the first speed for a second time duration after the first time duration. The wafer is rotated at a third speed that is higher than the second speed for a third time duration after the second time duration. A photoresist is dispensed on the wafer during the first time duration and at least a portion of a time interval that includes the second time duration and the third time duration. | 03-19-2015 |
Patent application number | Description | Published |
20080211026 | Coupling well structure for improving HVMOS performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 09-04-2008 |
20080248600 | METHOD AND DEVICE FOR WAFER BACKSIDE ALIGNMENT OVERLAY ACCURACY - A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure. | 10-09-2008 |
20090142898 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 06-04-2009 |
20110006366 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 01-13-2011 |
20110079846 | HIGH VOLTAGE DEVICES, SYSTEMS, AND METHODS FOR FORMING THE HIGH VOLTAGE DEVICES - A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type. | 04-07-2011 |
20110220995 | Semiconductor Device Having Multi-Thickness Gate Dielectric - A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided. | 09-15-2011 |
20120037987 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 02-16-2012 |
20130181285 | Lateral DMOS Device with Dummy Gate - An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor. | 07-18-2013 |
20130320430 | Vertical Power MOSFET and Methods of Forming the Same - A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. | 12-05-2013 |
20130320431 | Vertical Power MOSFET and Methods for Forming the Same - A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via. | 12-05-2013 |
20130320432 | Vertical Power MOSFET and Methods of Forming the Same - A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. The device further includes a MOS containing device. | 12-05-2013 |
20130320435 | Trench Power MOSFET - A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. | 12-05-2013 |
20130320437 | Power MOSFET and Methods for Forming the Same - A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region. | 12-05-2013 |
20140015037 | Novel Metal/Polysilicon Gate Trench Power Mosfet - The present disclosure relates to a power MOSFET device having a relatively low resistance hybrid gate electrode that enables good switching performance. In some embodiments, the power MOSFET device has a semiconductor body. An epitaxial layer is disposed on the semiconductor body. A hybrid gate electrode, which controls the flow of electrons between a source electrode and a drain electrode, is located within a trench extending into the epitaxial layer. The hybrid gate electrode has an inner region having a low resistance metal, an outer region having a polysilicon material, and a barrier region disposed between the inner region and the outer region. The low resistance of the inner region provides for a low resistance to the hybrid gate electrode that enables good switching performance for the power MOSFET device. | 01-16-2014 |
20140015038 | Apparatus and Method for Power MOS Transistor - A MOS transistor comprises a substrate, a first region formed over the substrate, a second region grown from the first region, a third region of formed in the second region, a first drain/source region formed in the third region, a first gate electrode formed in a first trench, a second drain/source region formed in the second region and on an opposite side of the first trench from the first drain/source region and a second trench coupled between the second drain/source region and the second region, wherein the second trench is of a same depth as the first trench. | 01-16-2014 |
20140015045 | Apparatus and Method for Power MOS Transistor - A power MOS transistor comprises a drain contact plug formed over a first side of a substrate, a source contact plug formed over a second side of the substrate and a trench formed between the first drain/source region and the second drain/source region. The trench comprises a first gate electrode, a second gate electrode, wherein top surfaces of the first gate electrode and the second gate electrode are aligned with a bottom surface of drain region. The trench further comprises a field plate formed between the first gate electrode and the second gate electrode, wherein the field plate is electrically coupled to the source region. | 01-16-2014 |
20140015047 | Integrated Circuit Having a Vertical Power MOS Transistor - An integrated circuit comprises a plurality of lateral devices and quasi vertical devices formed in a same semiconductor die. The quasi vertical devices include two trenches. A first trench is formed between a first drain/source region and a second drain/source region. The first trench comprises a dielectric layer formed in a bottom portion of the first trench and a gate region formed in an upper portion of the first trench. A second trench is formed on an opposite side of the second drain/source region from the first trench. The second trench is coupled between the second drain/source region and a buried layer, wherein the second trench is of a same depth as the first trench. | 01-16-2014 |
20140015048 | FinFET with Trench Field Plate - An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate. | 01-16-2014 |
20140045304 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 02-13-2014 |
20140162422 | Apparatus and Method for Power MOS Transistor - A MOS transistor comprises a substrate, a first region formed over the substrate, a second region grown from the first region, a third region of formed in the second region, a first drain/source region formed in the third region, a first gate electrode formed in a first trench, a second drain/source region formed in the second region and on an opposite side of the first trench from the first drain/source region and a second trench coupled between the second drain/source region and the second region, wherein the second trench is of a same depth as the first trench. | 06-12-2014 |
20140342520 | Vertical Power MOSFET and Methods for Forming the Same - A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via. | 11-20-2014 |
20150044837 | Trench Power MOSFET - A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. | 02-12-2015 |
20150056770 | Vertical Power MOSFET and Methods of Forming the Same - A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. | 02-26-2015 |
20150064868 | Apparatus and Method for Power MOS Transistor - A method comprises forming a first trench and a second trench, depositing a dielectric material in a lower portion of the first trench, depositing a gate electrode material in the second trench and an upper portion of the first trench, forming a first N+ region and a second N+ region through an ion implantation process, wherein the first N+ region and the second N+ region are on opposite sides of the first trench and forming an accumulation layer along a sidewall of the second trench. | 03-05-2015 |
20150104917 | Power MOSFET and Methods for Forming the Same - A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region. | 04-16-2015 |
20150118814 | FinFET with Trench Field Plate - An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate. | 04-30-2015 |