Patent application number | Description | Published |
20120065051 | OPTICAL GLASS FOR MOLD PRESS FORMING - The invention provides an optical glass for press molding which can satisfy all of the following requirements: (1) it contains no environmentally undesirable components; (2) it can easily achieve a low glass transition point; (3) it has a high refractive index and high dispersion; (4) it can easily provide a glass having an excellent visible light transmittance; and (5) it has excellent resistance to devitrification during preparation of a preform. The optical glass for press molding has a refractive index nd of 1.925 or more, an Abbe's number νd of 10 to 30, and a glass composition, in % by mass, of 20 to 80% Bi | 03-15-2012 |
20130090225 | OPTICAL GLASS AND OPTICAL ELEMENT - Provided is an optical glass which can satisfy all of the following requirements: (1) it contains no environmentally undesirable components; (2) it can easily achieve a low glass transition point; (3) it has a high refractive index and high dispersion; (4) it can easily provide a glass having a superior visible light transmittance; and (5) it has superior resistance to devitrification during preparation of a preform. The optical glass has a refractive index nd of 2.0 or more, an Abbe's number vd of 20 or less, a glass transition point of 450° C. or below, and a glass composition, in % by mass, of 70 to 90% Bi | 04-11-2013 |
20140045675 | OPTICAL GLASS FOR MOLD PRESS FORMING - The invention provides an optical glass for press molding which can satisfy all of the following requirements: (1) it contains no environmentally undesirable components; (2) it can easily achieve a low glass transition point; (3) it has a high refractive index and high dispersion; (4) it can easily provide a glass having an excellent visible light transmittance; and (5) it has excellent resistance to devitrification during preparation of a preform. The optical glass for press molding has a refractive index nd of 1.925 or more, an Abbe's number νd of 10 to 30, and a glass composition, in % by mass, of 20 to 80% Bi | 02-13-2014 |
20140144505 | GLASS USED IN OPTICAL ELEMENT FOR CONCENTRATING PHOTOVOLTAIC POWER GENERATION APPARATUS, OPTICAL ELEMENT FOR CONCENTRATING PHOTOVOLTAIC POWER GENERATION APPARATUS USING GLASS, AND CONCENTRATING PHOTOVOLTAIC POWER GENERATION APPARATUS - Provided are a glass which is used in an optical element for a concentrating photovoltaic power generation apparatus, has excellent weather resistance, and can be easily processed into a complicated shape; an optical element for a concentrating photovoltaic power generation apparatus using the glass; and a concentrating photovoltaic power generation apparatus. The glass used in an optical element for a concentrating photovoltaic power generation apparatus contains, in % by mass, 30 to 80% SiO | 05-29-2014 |
20140338748 | OPTICAL ELEMENT FOR LIGHT-CONCENTRATING SOLAR POWER GENERATION DEVICE, METHOD FOR PRODUCING SAME, AND LIGHT-CONCENTRATING SOLAR POWER GENERATION DEVICE - Provided is an optical element for a light-concentrating solar power generation device having excellent weather resistance and also excellent thermal shock resistance and crack resistance, a method for producing the same, and a light-concentrating solar power generation device including the optical element. An optical element for a light-concentrating solar power generation device, the optical element being made of a glass material having a compressive stress at a surface thereof. | 11-20-2014 |
Patent application number | Description | Published |
20100117719 | CHARGE PUMP CIRCUIT - A charge pump circuit includes a first plurality of capacitors, and a first precharge circuit. The first plurality of capacitors are connected in parallel to each other. The first plurality of capacitors receive clock signals to perform sequentially pumping operations which generate a first higher voltage from a power voltage supplied. The first precharge circuit precharges a predetermined number of capacitors in the first plurality of capacitors at the power voltage. The predetermined number is greater than one. | 05-13-2010 |
20100127761 | CHARGE PUMP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A charge pump circuit includes a plurality of capacitors connected in series via switch circuits, a plurality of pre-charge circuits that pre-charge the capacitors, respectively, and a control circuit that controls the switch circuits and the pre-charge circuits. The control circuit sequentially deactivates the pre-charge circuits from a pre-charge circuit allocated to the last stage capacitor to a pre-charge circuit allocated to the first stage capacitor in this order. Deactivation of each of the pre-charge circuits is performed after pre-charge of a parasitic capacitance component included in a latter stage capacitor than a corresponding capacitor is completed. With this method, a charge loss due to a parasitic capacitance is reduced, and at the same time, pre-charge of a parasitic capacitance component that is sequentially increased can be reliably performed. | 05-27-2010 |
20100165703 | SEMICONDUCTOR DEVICE FOR SUPPLYING STABLE VOLTAGE TO CONTROL ELECTRODE OF TRANSISTOR - A semiconductor device comprises an internal voltage generator circuit which includes a first transistor having a first and a second main electrode and a control electrode, a control circuit controlling a voltage between the second main electrode and the control electrode of the first transistor such that a voltage at the first main electrode of the first transistor remains at a predetermined voltage, and a second transistor having a first and a second main electrode and a control electrode. A voltage between the second main electrode and the control electrode of the first transistor is applied between the second main electrode and the control electrode of the second transistor. | 07-01-2010 |
Patent application number | Description | Published |
20100073077 | Boosting charge pump circuit - A boosting charge pump circuit includes a first charge pump circuit unit that includes: a first charge pump capacitor having first and second ends; a first driver supplying the first end of the first charge pump capacitor with a first clock signal having a first voltage amplitude; and a first switch having a first terminal electrically connected to the second end of the first charge pump capacitor, a second terminal operatively connected to an output terminal, and a third terminal. A second charge pump circuit unit includes: a second charge pump capacitor having a third end operatively connected to the output terminal and a fourth end; a second driver operating on a voltage at a power node thereof to supply the fourth end of the second charge pump capacitor with a second clock signal, the second clock signal having a second voltage amplitude defined by the voltage at the power node; and a second switch having a fourth terminal electrically connected to the third terminal of the first switch, a fifth terminal electrically connected to an internal power voltage supply line and a sixth terminal electrically connected to the power node of the second driver. The first terminal of the first switch is electrically connected to the second terminal of the first switch when the fifth terminal of the second switch is electrically connected to the sixth terminal of the second switch, and the first terminal of the first switch is electrically connected to the third terminal of the first switch when the fourth terminal of the second switch is electrically connected to the sixth terminal of the second switch. | 03-25-2010 |
20100091597 | SEMICONDUCTOR DEVICE - A semiconductor device includes an internal voltage generating circuit which includes a first voltage generating circuit, a second voltage generating circuit having a higher current supply capability than the first voltage generating circuit, and a control circuit that controls switching between activation and inactivation of the second voltage generating circuit, using a first internal signal of the first voltage generating circuit. | 04-15-2010 |
20100118625 | CHARGE PUMP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A charge pump circuit includes a first charge pump unit that includes a first capacitor and a second capacitor connected in parallel and generates a first charge pump voltage in the second capacitor by pumping the first capacitor, and a second charge pump unit that includes a third capacitor connected to the second capacitor in series and generates a second charge pump voltage in the second capacitor by further pumping the first charge pump voltage charged in the second capacitor via the third capacitor. In this manner, by pumping the latter stage capacitor from among the capacitors connected in parallel by a parallel connection method, the voltage applied between the capacitor electrodes of the latter stage capacitor is lowered. | 05-13-2010 |
20100127766 | Semiconductor apparatus - A semiconductor apparatus includes a first internal voltage generator generating a first internal voltage in response to an external power supply voltage, a second internal voltage generator generating a second internal voltage in response to the external power supply voltage, the second internal voltage is larger in absolute value than the first internal voltage, and a preset signal generating circuit responding to a power-on of the external power supply voltage to the semiconductor apparatus and generating first and second preset signals which bring the first and second internal voltage generators into respective initial states, generation of the second preset signal is stopped after stopping generation of the first preset signal, in which the first internal voltage generator is released from its initial state in response to the stopping the generation of the first preset signal to be allowed to generate the first internal voltage, the second internal voltage generator is released from its initial state in response to the stopping the generation of the second preset signal to be allowed to generate the first internal voltage, and the second internal voltage is generated after generation of the first internal voltage. | 05-27-2010 |
20110175644 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes a first circuit block connected between first and second power lines, a logic circuit that receives an output signal of the first circuit block that is connected between the first power line and a fourth power line or a third power line and the second power line, and a second circuit block that receives an output signal of the logic circuit that is connected between the third and fourth power lines. In an active state, a first potential is supplied and in a standby state, a second potential lower than the first potential is supplied between the first and second power lines. In any of the active state and the standby state, the first potential is supplied between the third and fourth power lines. With this configuration, speeding-up of a critical path can be realized while maintaining a subthreshold current low. | 07-21-2011 |
20110175660 | Semiconductor device, data transmission system and method of controlling semiconductor device - A semiconductor device includes an amplifier section that receives a small-amplitude signal in which data is updated in synch with a clock, and an output section coupled to the output of the amplifier section. In synch with the clock, the amplifier section increases the current of a current source at timings at which the logic level of the small-amplitude signal is capable of undergoing a transition, and decreases the current at timings at which there is no transition. In synch with the clock, the output section drives a load by decreasing output impedance at timings at which the logic level of output data of the amplifier section is capable of undergoing a transition, and prevents flow of a through-current by increasing output impedance at timings at which the logic level does not undergo a transition. | 07-21-2011 |
20110175673 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A pair of power nodes of a logic circuit that needs to output a high level at the time of standby is connected to third and fifth dummy power lines and a pair of power nodes of a logic circuit that needs to output a low level at the time of standby are connected to second and sixth dummy power lines. Fourth, third, sixth, and fifth potentials of the second, third, fifth, and sixth dummy power lines satisfy fourth potentialfifth potential>second potential. With this configuration, a leakage current flowing between a substrate and a gate of a transistor that becomes on at the time of standby, and a leakage current flowing between the substrate and a drain of a transistor that becomes off at the time of standby can be reduced. | 07-21-2011 |
20110179210 | Semiconductor device and data processing system - A semiconductor device includes: first transmission wirings each transmitting a small-amplitude signal between one of a plurality of first drivers and one of a plurality of receivers; a second transmission wiring transmitting a reference signal connected to each of the plurality of receivers; and a second driver outputting the reference signal with an impedance higher than an impedance with which each of the first drivers outputs the small-amplitude signal. The second transmission wiring is arranged between first and second power supply wirings corresponding to first and second potentials of the small-amplitude signal. The first and second potentials are supplied to each of the first drivers. The plurality of first transmission wirings are arranged close to each other, without being sandwiched between the first and second power supply wirings. | 07-21-2011 |
20120139508 | SEMICONDUCTOR APPARATUS - A device includes a first internal voltage generation circuit generating a first internal voltage in response to an external power supply voltage, a second internal voltage generation circuit generating a second internal voltage in response to the external power supply voltage, the second internal voltage being different in voltage level from the first internal voltage, and a preset signal generation circuit responding to a power-on of the external power supply voltage to the device and generating, independently of the first internal voltage, first and second preset signals that bring the first and the second internal voltage generation circuits into respective initial states, the preset signal generating circuit stopping generation of the first preset signal when the external power supply voltage reaches a first voltage level and stopping generation of the second preset signal when the external power supply voltage reaches a second voltage level different from the first voltage level. | 06-07-2012 |
20120257437 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, and second transistors connected between the first and second interconnects in series with each other on both sides of the variable resistance element, and a power supply circuit unit that delivers the power supply to a control electrode of the first transistor. The power supply circuit unit supplies the power of a first power supply when the variable resistance element is to make transition to the first resistance value and the power supply circuit unit supplies the power of a second power supply when the variable resistance element is to make transition to the second resistance value, thereby allowing transitioning of the resistance values of the variable resistance element | 10-11-2012 |
20130278286 | SEMICONDUCTOR DEVICE HAVING CALIBRATION CIRCUIT THAT ADJUSTS IMPEDANCE OF OUTPUT BUFFER - Disclosed herein is a device that includes: a data terminal; an output buffer coupled to the data terminal, the output buffer including a first output unit having a plurality of first output transistors of a first conductivity type and a second output unit having a plurality of second output transistors of a second conductivity type; and a calibration circuit including a first code generation unit that generates a first control code that controls an impedance of the first output unit by performing a first calibration operation based on an impedance of a first reference unit and a second code generation unit that generates a second control code that controls an impedance of the second output unit by performing a second calibration operation based on an impedance of a second reference unit. The calibration circuit performs the first and second calibration operations in parallel. | 10-24-2013 |