Lee, Ichon
Dong Ryeol Lee, Ichon KR
Patent application number | Description | Published |
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20090117748 | METHOD FOR MANUFACTURING A PHASE CHANGE MEMORY DEVICE CAPABLE OF IMPROVING THERMAL EFFICIENCY OF PHASE CHANGE MATERIAL - A method for manufacturing a phase change memory device, capable of improving reset current characteristics of a phase change layer by preventing thermal loss of the phase change layer. An interlayer dielectric layer having a lower electrode contact is formed on a semiconductor substrate. A phase change layer and an upper electrode layer are sequentially formed on the interlayer dielectric layer. Then, an upper electrode and a phase change pattern are formed by etching predetermined portions of the upper electrode layer and the phase change layer using an etching gas having chlorine gas. | 05-07-2009 |
20090321705 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate, a first conductive pattern formed on the semiconductor substrate, a second conductive pattern contacting an upper surface of the first conductive pattern and having a diameter less than a diameter of the first conductive pattern, and a phase change material layer contacting the second conductive pattern. | 12-31-2009 |
Eun Souk Lee, Ichon KR
Patent application number | Description | Published |
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20080225605 | LATCH STRUCTURE AND BIT LINE SENSE AMPLIFIER STRUCTURE INCLUDING THE SAME - A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line. | 09-18-2008 |
20100097873 | LATCH STRUCTURE AND BIT LINE SENSE AMPLIFIER STRUCTURE INCLUDING THE SAME - A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line. | 04-22-2010 |
Geun Il Lee, Ichon KR
Patent application number | Description | Published |
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20090257285 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes an input buffering block configured to buffer an input signal transmitted from an input pin, a latch block configured to latch the input signal buffered by the input buffering block, a defect discriminating block configured to discriminate whether or not the input signal latched by the latch block is defective signal in response to a test mode signal, and a data output buffer configured to buffer an output signal of the defect discriminating block to transmit it to a data output pin, wherein the input signal is one of an input command signal and an input address signal. | 10-15-2009 |
Hyeng Ouk Lee, Ichon KR
Patent application number | Description | Published |
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20090040847 | OUTPUT ENABLE SIGNAL GENERATING CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal. | 02-12-2009 |
20110085395 | OUTPUT ENABLE SIGNAL GENERATING CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal. | 04-14-2011 |
Hyung-Dong Lee, Ichon KR
Patent application number | Description | Published |
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20090046528 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated. | 02-19-2009 |
20100264945 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated. | 10-21-2010 |
Hyung Suk Lee, Ichon KR
Patent application number | Description | Published |
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20090321705 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate, a first conductive pattern formed on the semiconductor substrate, a second conductive pattern contacting an upper surface of the first conductive pattern and having a diameter less than a diameter of the first conductive pattern, and a phase change material layer contacting the second conductive pattern. | 12-31-2009 |
Jee Eun Lee, Ichon KR
Patent application number | Description | Published |
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20080212394 | WRITE DRIVING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A write driving circuit includes a plurality of driving units that write data corresponding to detection signals on memory banks, and at least one detecting unit that detects data input from the outside, and outputs the detection signals to two or more driving units among the plurality of driving units. | 09-04-2008 |
20080253210 | SEMICONDUCTOR MEMORY APPARATUS - Disclosed is a semiconductor memory apparatus capable of improving precharge performance. The semiconductor memory apparatus includes a plurality of memory banks, data input/output lines commonly connected to the memory banks, and a plurality of precharge circuit units connected to the data input/output lines and aligned in an extension direction of the data input/output lines while being spaced apart from each other by a predetermined distance. | 10-16-2008 |
Jeong Hun Lee, Ichon KR
Patent application number | Description | Published |
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20100077268 | APPARATUS AND METHOD FOR TESTING SETUP/HOLD TIME - An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units. | 03-25-2010 |
Jeong Woo Lee, Ichon KR
Patent application number | Description | Published |
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20090046526 | WORD LINE DRIVING CIRCUIT AND METHOD OF TESTING A WORD LINE USING THE WORD LINE DRIVING CIRCUIT - A method of testing a word line using a word line driving circuit comprising: activating a word line by activating a word line driving signal; floating the word line by activating a test mode signal after the activating of the word line; recording data having a predetermined logic value into a memory cell by inputting a write command while the word line is floated; and reading out data from the memory cell by inputting a read command after the recording of data. | 02-19-2009 |
20100091599 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes first and second bank blocks, a mode generator configured to generate a chip select mode signal used to control an operational mode of the first and second bank blocks, and a controller configured to drive the first and second bank blocks in response to the chip select mode signal, first and second select signals, and a predetermined address signal that are used to control driving of the first and second bank blocks, wherein the controller receives the chip select mode signal having a level used to determine a single chip mode to control operation of the first and second bank blocks in one rank unit, and the first and second bank blocks are selectively activated by using the predetermined address signal. | 04-15-2010 |
Joong-Ho Lee, Ichon KR
Patent application number | Description | Published |
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20080307170 | MEMORY MODULE AND MEMORY SYSTEM - A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to each rank by using signals of the first pin group. | 12-11-2008 |
20090147614 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory includes a cell mat configured to include a plurality of memory cells to which a first bit line pair or a second bit line pair is connected; a sense amplifier configured to amplify a positive sensing line and a negative sensing line in response to a first bit line equalize signal; a column selecting unit configured to connect the positive sensing line and the negative sensing line to a first data bus and a second data bus, respectively, in response to a column selection signal; and a share control unit configured to connect the positive sensing line and a positive first bit line of the first bit line pair or a positive second bit line of the second bit line pair in response to a second bit line equalize signal, a positive share control signal and a negative share control signal. | 06-11-2009 |
Jun Woo Lee, Ichon KR
Patent application number | Description | Published |
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20080252332 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A semiconductor integrated circuit includes an ODT signal generator that receives an ODT command signal, an ODT reset signal, and an ODT calibration end signal to generate an ODT control signal according to the phase of the ODT calibration end signal, and an ODT resistance adjusting unit that is to perform an on-die termination operation in response to the ODT control signal. | 10-16-2008 |
20090121786 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit. | 05-14-2009 |
Kang Seol Lee, Ichon KR
Patent application number | Description | Published |
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20080225605 | LATCH STRUCTURE AND BIT LINE SENSE AMPLIFIER STRUCTURE INCLUDING THE SAME - A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line. | 09-18-2008 |
20100097873 | LATCH STRUCTURE AND BIT LINE SENSE AMPLIFIER STRUCTURE INCLUDING THE SAME - A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line. | 04-22-2010 |
Kang Youl Lee, Ichon KR
Patent application number | Description | Published |
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20080303574 | INTERNAL CLOCK DRIVER CIRCUIT - An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal. | 12-11-2008 |
20090003500 | CIRCUIT FOR OUTPUTTING DATA OF SEMICONDUCTOR MEMORY APPARATUS - A data output circuit of a semiconductor memory apparatus can include a clock synchronization unit (which is driven by a power supply voltage) that can be configured to receive data and output first synchronization data and second synchronization data in synchronization with a clock; a voltage converting unit that can be configured to convert the first and second synchronization data, which can swing between the power supply voltage and a ground voltage, into first and second converted data, which can swing between an I/O power supply voltage and the ground voltage; and a data output driver, which is driven by the I/O power supply voltage, for outputting the first converted data and the second converted data as output data. | 01-01-2009 |
20090168547 | APPARATUS AND METHODS FOR A DATA INPUT CIRCUIT FOR A SEMICONDUCTOR MEMORY APPARATUS - A data input circuit for a semiconductor memory apparatus includes a data latch block that, according to a data strobe signal, latches data and outputs the latched data; a data output controlling unit that determines a phase difference between the data strobe signal and a clock signal, and activates a data output control signal; and a data delay block that, when the data output control signal is activated, delays the data output from the data latch block for a predetermined time, and outputs the delayed data. | 07-02-2009 |
20100019813 | INTERNAL CLOCK DRIVER CIRCUIT - An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal. | 01-28-2010 |
Kwang Su Lee, Ichon KR
Patent application number | Description | Published |
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20090122850 | TEST CIRCUIT CAPABLE OF MASKING DATA AT READ OPERATION AND METHOD FOR CONTROLLING THE SAME - A test circuit capable of reducing the number of data I/O pins of a tester at a read operation includes a data masking control unit for masking a part of output data in response to an activation of one of an upper data masking signal to control a group of upper data pins and a lower data masking signal to control a group of lower data pins when a test mode signal is activated at a read operation. | 05-14-2009 |
20090167388 | DELAY LOCKED LOOP CIRCUIT AND CONTROL METHOD OF THE SAME - A delay locked loop capable of preventing delay locking time from being increased, even if the operational environment fluctuates. The delay locked loop circuit includes a delay line for delaying and outputting a reference clock signal, a phase detection unit for detecting a phase difference between the reference clock signal and an output signal of the delay line and then outputting a phase detection signal and a first delay mode decision signal, a control unit for outputting a delay control signal to control the delay line according to the phase detection signal and a second delay mode decision signal, and an error decision unit for detecting an error of the first delay mode decision signal according to the delay control signal and the output signal of the delay line and outputting the second delay mode decision signal according to a result of the error detection. | 07-02-2009 |
20100213995 | DELAY LOCKED LOOP CIRCUIT AND CONTROL METHOD OF THE SAME - A delay locked loop capable of preventing delay locking time from being increased, even if the operational environment fluctuates. The delay locked loop circuit includes a delay line for delaying and outputting a reference clock signal, a phase detection unit for detecting a phase difference between the reference clock signal and an output signal of the delay line and then outputting a phase detection signal and a first delay mode decision signal, a control unit for outputting a delay control signal to control the delay line according to the phase detection signal and a second delay mode decision signal, and an error decision unit for detecting an error of the first delay mode decision signal according to the delay control signal and the output signal of the delay line and outputting the second delay mode decision signal according to a result of the error detection. | 08-26-2010 |
Seong Jun Lee, Ichon KR
Patent application number | Description | Published |
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20090302912 | DUTY CYCLE CORRECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A duty cycle correction circuit of a semiconductor memory apparatus includes a duty ratio correcting unit configured to correct a duty ratio of a clock signal according to levels of a first reference voltage and a second reference voltage, and to output the clock signal as a correction clock signal, a duty ratio detecting unit configured to count first and second counting signals in response to a duty ratio of the correction clock signal when a pump enable signal is enabled, a pump enable signal generating unit configured to generate the pump enable signal in response to the duty ratio of the correction clock signal, and a reference voltage generating unit configured to generate the first and second reference voltages in response to the first and second counting signals. | 12-10-2009 |