Patent application number | Description | Published |
20080210925 | THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS - A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration. | 09-04-2008 |
20080224118 | HEAT-SHIELDED LOW POWER PCM-BASED REPROGRAMMABLE EFUSE DEVICE - An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes. | 09-18-2008 |
20080285335 | PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES USING EXTERNALLY HEATED PHASE CHANGE MATERIAL - A programmable phase change material (PCM) structure includes a heater element formed at a transistor gate level of a semiconductor device, the heater element further including a pair of electrodes connected by a thin wire structure with respect to the electrodes, the heater element configured to receive programming current passed therethrough, a layer of phase change material disposed on top of a portion of the thin wire structure, and sensing circuitry configured to sense the resistance of the phase change material. | 11-20-2008 |
20090033358 | PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap. | 02-05-2009 |
20090033360 | PROGRAMMABLE VIA DEVICES WITH AIR GAP ISOLATION - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; a heater over the first dielectric layer; an air gap separating at least a portion of the heater from the first dielectric layer; an isolation layer over the first dielectric layer covering at least a portion of the heater; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap. | 02-05-2009 |
20090039331 | PHASE CHANGE MATERIAL STRUCTURES - Structures including a phase change material are disclosed. The structure may include a first electrode; a second electrode; a phase change material electrically connecting the first electrode and the second electrode for passing a current therethrough; and a tantalum nitride heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM). | 02-12-2009 |
20090045388 | PHASE CHANGE MATERIAL STRUCTURE AND RELATED METHOD - A structure including a phase change material and a related method are disclosed. The structure may include a first electrode; a second electrode; a third electrode; a phase change material electrically connecting the first, second and third electrodes for passing a first current through two of the first, second and third electrodes; and a refractory metal barrier heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM). | 02-19-2009 |
20090065761 | PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES IN BEOL REGIONS USING EXTERNALLY HEATED PHASE CHANGE MATERIAL - A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via. | 03-12-2009 |
20090072213 | Programmable Via Structure for Three Dimensional Integration Technology - A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof | 03-19-2009 |
20090262572 | MULTILAYER STORAGE CLASS MEMORY USING EXTERNALLY HEATED PHASE CHANGE MATERIAL - A multi-layer, phase change material (PCM) memory apparatus includes a plurality of semiconductor layers sequentially formed over a base substrate, wherein each layer comprises an array of memory cells formed therein, each memory cell further including a PCM element, a first diode serving as a heater diode in thermal proximity to the PCM element and configured to program the PCM element to one of a low resistance crystalline state and a high resistance amorphous state, and a second diode serving a sense diode for a current path used in reading the state of the PCM element; the base substrate further including decoding, programming and sensing circuitry formed therein, with each of the plurality of semiconductor layers spaced by an insulating layer; and intralayer wiring for communication between the base substrate circuitry and the array of memory cells in each of the semiconductor layers. | 10-22-2009 |
20090310472 | METHOD AND STRUCTURE FOR ULTRA-HIGH DENSITY, HIGH DATA RATE FERROELECTRIC STORAGE DISK TECHNOLOGY USING STABILIZATION BY A SURFACE CONDUCTING LAYER - A method and structure for a ferroelectric storage medium, includes a metallic underlayer and a ferroelectric data layer over the metallic underlayer. A layer over the ferroelectric data layer has a charge migration rate faster than a charge migration rate of the ferroelectric data layer. | 12-17-2009 |
20090315010 | THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS - A three-terminal switching device for use in integrated circuit devices, including a phase change material (PCM) disposed in contact between a first terminal and a second terminal; a heating device disposed in direct electrical contact between said second terminal and a third terminal, said heating device positioned proximate said PCM, and configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate said heater from said PCM material, and said heater from said first terminal. | 12-24-2009 |
20090321710 | THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS - A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration. | 12-31-2009 |
20100073997 | PIEZO-DRIVEN NON-VOLATILE MEMORY CELL WITH HYSTERETIC RESISTANCE - A piezoelectrically programmed, non-volatile memory cell structure includes a programmable piezo-resistive hysteretic material (PRHM) that is capable of being interconverted between a low resistance state and high resistance state through applied pressure cycling thereto; a piezoelectric material mechanically coupled to the PHRM such that an applied voltage across the piezoelectric material results in one of a tensile or compressive stress applied to the PRHM, depending upon the polarity of the applied voltage; and one or more electrodes in electrical communication with the PRHM, wherein the one or more electrodes are configured to provide a write programming current path through the piezoelectric material and a read current path through the PRHM. | 03-25-2010 |
20100328984 | PIEZO-EFFECT TRANSISTOR DEVICE AND APPLICATIONS - A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode and a third electrode, wherein the first electrode comprises a gate terminal, the second electrode comprises a common terminal, and the third electrode comprises an output terminal such that an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material. | 12-30-2010 |
20110119215 | HARDWARE ANALOG-DIGITAL NEURAL NETWORKS - An analog-digital crosspoint-network includes a plurality of rows and columns, a plurality of synaptic nodes, each synaptic node of the plurality of synaptic nodes disposed at an intersection of a row and column of the plurality of rows and columns, wherein each synaptic node of the plurality of synaptic nodes includes a weight associated therewith, a column controller associated with each column of the plurality of columns, wherein each column controller is disposed to enable a weight change at a synaptic node in communication with said column controller, and a row controller associated with each row of the plurality of rows, wherein each row controller is disposed to control a weight change at a synaptic node in communication with said row controller. | 05-19-2011 |
20110122682 | High Density Low Power Nanowire Phase Change Material Memory Device - A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction. | 05-26-2011 |
20110133603 | COUPLING PIEZOELECTRIC MATERIAL GENERATED STRESSES TO DEVICES FORMED IN INTEGRATED CIRCUITS - A coupling structure for coupling piezoelectric material generated stresses to an actuated device of an integrated circuit includes a rigid stiffener structure formed around a piezoelectric (PE) material and the actuated device, the actuated device comprising a piezoresistive (PR) material that has an electrical resistance dependent upon an applied pressure thereto; and a soft buffer structure formed around the PE material and PR material, the buffer structure disposed between the PE and PR materials and the stiffener structure, wherein the stiffener structure clamps both the PE and PR materials to a substrate over which the PE and PR materials are formed, and wherein the soft buffer structure permits the PE material freedom to move relative to the PR material, thereby coupling stress generated by an applied voltage to the PE material to the PR material so as change the electrical resistance of the PR material. | 06-09-2011 |
20110217836 | Programmable Via Devices in Back End of Line Level - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap. | 09-08-2011 |
20110308949 | NANO-FLUIDIC FIELD EFFECTIVE DEVICE TO CONTROL DNA TRANSPORT THROUGH THE SAME - The present invention provides a nano-fluidic field effective device. The device includes a channel having a first side and a second side, a first set of electrodes adjacent to the first side, a second set of electrodes adjacent to the second side, a control unit for applying electric potentials to the electrodes and a fluid within the channel containing a charge molecule. The first set of electrodes is disposed such that application of electric potentials produces a spatially varying electric field that confines a charged molecule within a predetermined area of said channel. The second set of electrodes is disposed such that application of electric potentials relative to the electric potentials applied to the first set of electrodes creates an electric field that confines the charged molecule to an area away from the second side of the channel. | 12-22-2011 |
20120000516 | Graphene Solar Cell - A solar cell includes a semiconductor portion, a graphene layer disposed on a first surface of the semiconductor portion, and a first conductive layer patterned on the graphene layer, the first conductive layer including at least one bus bar portion and a plurality of fingers extending from the at least one bus bar portion. | 01-05-2012 |
20120000521 | Graphene Solar Cell And Waveguide - A solar cell includes a semiconductor portion, a graphene layer disposed on a first surface of the semiconductor portion, and a first conductive layer patterned on the graphene layer, the first conductive layer including at least one bus bar portion, a plurality of fingers extending from the at least one bus bar portion, and a refractive layer disposed on the first conductive layer. | 01-05-2012 |
20120153248 | THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS - A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration. | 06-21-2012 |
20120225527 | HIGH DENSITY LOW POWER NANOWIRE PHASE CHANGE MATERIAL MEMORY DEVICE - A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction. | 09-06-2012 |
20120270353 | COUPLING PIEZOELECTRIC MATERIAL GENERATED STRESSES TO DEVICES FORMED IN INTEGRATED CIRCUITS - A coupling structure for coupling piezoelectric material generated stresses to an actuated device of an integrated circuit includes a rigid stiffener structure formed around a piezoelectric (PE) material and the actuated device, the actuated device comprising a piezoresistive (PR) material that has an electrical resistance dependent upon an applied pressure thereto; and a soft buffer structure formed around the PE material and PR material, the buffer structure disposed between the PE and PR materials and the stiffener structure, wherein the stiffener structure clamps both the PE and PR materials to a substrate over which the PE and PR materials are formed, and wherein the soft buffer structure permits the PE material freedom to move relative to the PR material, thereby coupling stress generated by an applied voltage to the PE material to the PR material so as change the electrical resistance of the PR material. | 10-25-2012 |
20130009668 | 4-TERMINAL PIEZOELECTRONIC TRANSISTOR (PET) - A 4-terminal piezoelectronic transistor (PET) which includes a piezoelectric (PE) material disposed between first and second electrodes; an insulator material disposed on the second electrode; a third electrode disposed on the insulator material and a piezoresistive (PR) material disposed between the third electrode and a fourth electrode. An applied voltage across the first and second electrodes causing a pressure from the PE material to be applied to the PR material through the insulator material, the electrical resistance of the PR material being dependent upon the pressure applied by the PE material. The first and second electrodes are electrically isolated from the third and fourth electrodes. Also disclosed are logic devices fabricated from 4-terminal PETs and a method of fabricating a 4-terminal PET. | 01-10-2013 |
20130028823 | DOPED, PASSIVATED GRAPHENE NANOMESH, METHOD OF MAKING THE DOPED, PASSIVATED GRAPHENE NANOMESH, AND SEMICONDUCTOR DEVICE INCLUDING THE DOPED, PASSIVATED GRAPHENE NANOMESH - A method of making a semiconductor device, includes providing a graphene sheet, creating a plurality of nanoholes in the graphene sheet to form a graphene nanomesh, the graphene nanomesh including a plurality of carbon atoms which are formed adjacent to the plurality of nanoholes, passivating a dangling bond on the plurality of carbon atoms by bonding a passivating element to the plurality of carbon atoms, and doping the passivated graphene nanomesh by bonding a dopant to the passivating element. | 01-31-2013 |
20130033918 | METHOD AND STRUCTURE FOR ULTRA-HIGH DENSITY, HIGH DATA RATE FERROELECTRIC STORAGE DISK TECHNOLOGY USING STABILIZATION BY A SURFACE CONDUCTING LAYER - A electrometric access head includes a supporting substrate and a plurality of read elements mounted on the supporting substrate. Each read element includes an electrometric sensor for detection of a sign of polarization of domains within a ferroelectric data layer of a ferroelectric storage medium. The ferroelectric data layer serves as a layer for storing information as bits defined by the signs of polarization of domains within the ferroelectric data layer, each polarized domain including a volume dipole polarization within the ferroelectric data layer and including an area of bound charge on and adjacent to a surface of the ferroelectric data layer. | 02-07-2013 |
20130164882 | TRANSPARENT CONDUCTING LAYER FOR SOLAR CELL APPLICATIONS - Disclosed is a method which includes forming a bottom metallic electrode on an insulating substrate; forming a semiconductor junction on the metallic electrode; forming a transparent conducting overlayer in contact with the semiconductor junction; and forming a metallic layer in contact with the transparent conducting overlayer, wherein the metallic layer is formed by a plating process. The plating process may be an electroplating process or an electroless plating process. The transparent conducting overlayer may be carbon nanotubes or graphene. The semiconductor junction may be a p-i-n semiconductor junction, a p-n semiconductor junction, an n-p semiconductor junction or an n-i-p semiconductor junction. | 06-27-2013 |
20130164888 | Graphene Solar Cell - A solar cell includes a semiconductor portion, a graphene layer disposed on a first surface of the semiconductor portion, and a first conductive layer patterned on the graphene layer, the first conductive layer including at least one bus bar portion and a plurality of fingers extending from the at least one bus bar portion. | 06-27-2013 |
20130313501 | DRIFT-INSENSITIVE OR INVARIANT MATERIAL FOR PHASE CHANGE MEMORY - A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit. | 11-28-2013 |
20130314983 | DRIFT-INSENSITIVE OR INVARIANT MATERIAL FOR PHASE CHANGE MEMORY - A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit. | 11-28-2013 |
20140169078 | PIEZOELECTRONIC MEMORY - A memory element includes a first piezotronic transistor coupled to a second piezotronic transistor; the first and second piezotronic transistors each comprising a piezoelectric (PE) material and a piezoresistive (PR) material, wherein an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material. | 06-19-2014 |
20140253452 | WIRELESS KEYBOARD - Embodiments include a wireless keyboard having a plurality of keys and a plurality of radio frequency identification (RFID) tags, wherein each of the plurality of RFID tags are coupled to one of the plurality of keys. Each of the RFID tags are configured to transmit a signal when one of the plurality of keys coupled to RFID tag is pressed. | 09-11-2014 |
20150068902 | NANO-FLUIDIC FIELD EFFECTIVE DEVICE TO CONTROL DNA TRANSPORT THROUGH THE SAME - The present invention provides a nano-fluidic field effective device. The device includes a channel having a first side and a second side, a first set of electrodes adjacent to the first side, a second set of electrodes adjacent to the second side, a control unit for applying electric potentials to the electrodes and a fluid within the channel containing a charge molecule. The first set of electrodes is disposed such that application of electric potentials produces a spatially varying electric field that confines a charged molecule within a predetermined area of said channel. The second set of electrodes is disposed such that application of electric potentials relative to the electric potentials applied to the first set of electrodes creates an electric field that confines the charged molecule to an area away from the second side of the channel. | 03-12-2015 |
20150069305 | DOPED, PASSIVATED GRAPHENE NANOMESH, METHOD OF MAKING THE DOPED, PASSIVATED GRAPHENE NANOMESH, AND SEMICONDUCTOR DEVICE INCLUDING THE DOPED, PASSIVATED GRAPHENE NANOMESH - A doped, passivated graphene nanomesh includes a graphene nanomesh, a plurality of nanoholes formed in a graphene sheet, and a plurality of carbon atoms which are formed adjacent to the plurality of nanoholes; a passivating element bonded to the plurality of carbon atoms; and a dopant bonded to the passivating element, the dopant comprising one of an electron-donating element for making the graphene nanomesh an n-doped graphene nanomesh, and an electron-accepting element for making the graphene nanomesh a p-doped graphene nanomesh. | 03-12-2015 |