Hsiao-Chu
Hsiao-Chu Chao, Baoshan Township TW
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20140189635 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER-READABLE MEDIUM - A semiconductor device design system comprising at least one processor is configured to define a resistance-capacitance (RC) extraction tool for determining a distance between first and second through-semiconductor-vias extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second through-semiconductor-vias in the semiconductor substrate. The semiconductor device design system comprising the at least one processor is also configured to extract parasitic parameters of a coupling in the semiconductor substrate based on the distance determined by the RC extraction tool and a model of the coupling included in a simulation tool. | 07-03-2014 |
Hsiao-Chu Chen, Caotun Township TW
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20130181300 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 07-18-2013 |
20130187206 | FinFETs and Methods for Forming the Same - A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions. | 07-25-2013 |
20130228876 | FinFET Design with LDD Extensions - System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions. | 09-05-2013 |
20140103453 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 04-17-2014 |
Hsiao-Chu Huang, Taipei County TW
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20100166890 | ANTITUSSIVE COMPOSITION AND METHOD FOR MAKING THE SAME - An antitussive composition is provided. A pharmaceutical composition for relieving, preventing and/or treating a cough includes a sufficient amount of the | 07-01-2010 |
Hsiao-Chu Huang, Taipei City TW
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20150079202 | USE OF PATCHOULI EXTRACT IN THE PREPARATION OF COMPOSITIONS WITH AN ANTI-MICROORGANISM EFFECT - The present invention provides a method or composition for inhibiting the infection of a microorganism in a subject, using a | 03-19-2015 |
Hsiao-Chu Lin, Taipei Hsien TW
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20090045903 | INDUCTOR STRUCTURE - An inductor structure including a coil layer and at least a gain lead is disclosed. The coil layer is disposed over a substrate and has a plurality of coil turns, wherein one of the coil turns is grounded. The gain lead is disposed under at least one of the inner side and the outer side of the grounded coil turn and is electrically connected in parallel to the grounded coil turn. The width of the gain lead is less than the width of the grounded coil turn. | 02-19-2009 |
20090167476 | INDUCTOR STRUCTURE - An inductor structure disposed over a substrate and including a coil layer is provided. The coil layer has a plurality of coil turns electrically connected with each other. An innermost coil turn of the coil layer has a portion with a narrower width in a region with a higher magnetic flux density than that in the other region with lower magnetic flux density. | 07-02-2009 |
Hsiao-Chu Lin, Taipei County TW
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20090115562 | SPIRAL INDUCTOR - A spiral inductor is provided. The spiral inductor includes a first spiral conductive trace with at least one turn, a second spiral conductive trace, and a connector. The first spiral conductive trace comprises an outer end and an inner end. The second spiral conductive trace surrounds a portion of the outermost turn of the first spiral conductive trace, and comprises a first end and a second end. The connector electrically connects to the inner end and the first end. | 05-07-2009 |