Patent application number | Description | Published |
20080276034 | Design Structure for Transmitting Data in an Integrated Circuit - A design structure, which may be generated by a fabless design company, for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores. | 11-06-2008 |
20090045839 | ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE - A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process. The invention is also directed to a design structure on which a circuit resides. | 02-19-2009 |
20090183134 | DESIGN STRUCTURE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES - A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. | 07-16-2009 |
20090183135 | Method and Device for Identifying and Implementing Flexible Logic Block Logic for Easy Engineering Changes - A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). | 07-16-2009 |
20100017773 | Method for Minimizing Impact of Design Changes For Integrated Circuit Designs - A method is provided for updating an existing netlist to reflect a design change. A design incorporating the design change and the existing netlist are provided to a synthesis tool. The design and the existing netlist are processed with the synthesis tool reusing logic structures from the existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change. | 01-21-2010 |
20120167022 | METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES - A chip design methodology and an integrated circuit chip. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). | 06-28-2012 |
20140028365 | RING OSCILLATOR - Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided. | 01-30-2014 |
20140132290 | FLEXIBLE PERFORMANCE SCREEN RING OSCILLATOR WITHIN A SCAN CHAIN - Aspects of the invention provide for a flexible performance screen ring oscillator (PSRO) integrated within a scan chain. In one embodiment, a circuit structure to create the flexible PSRO includes: a plurality of programmable scan chain elements; and a forward test scan chain path through the plurality of scan chain elements; wherein each of the programmable scan chain elements includes additional circuitry for a backward path, such that the backward path and the forward test scan chain path are combined to create the PSRO. | 05-15-2014 |
20140195196 | CHIP PERFORMANCE MONITORING SYSTEM AND METHOD - Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies. | 07-10-2014 |