Patent application number | Description | Published |
20120326305 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved. | 12-27-2012 |
20130026657 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The semiconductor package includes a dielectric layer having opposite first and second surfaces; a semiconductor chip disposed on the first surface; at least two conductive pads embedded in and exposed from the first surface of the dielectric layer, and electrically connected to the semiconductor chip; a plurality of ball-implanting pads formed on the second surface of the dielectric layer; and a plurality of conductive pillars formed in the dielectric layer, each of the conductive pillars having a first end electrically connected to one of the ball-implanting pads and a second end opposing the first end and electrically connected to one of the conductive pads. Through the installation of the conductive pillars, it is not necessary for the ball-implanting pads to be associated with the conductive pads in position, and the semiconductor package thus has an adjustable ball-implanting area. | 01-31-2013 |
20130228921 | SUBSTRATE STRUCTURE AND FABRICATION METHOD THEREOF - A substrate structure includes a substrate body and a plurality of conductive pads formed on the substrate body and each having a first copper layer, a nickel layer, a second copper layer and a gold layer sequentially stacked. The thickness of the second copper layer is less than the thickness of the first copper layer. As such, the invention effectively enhances the bonding strength between the conductive pads and solder balls to be mounted later on the conductive pads, and prolongs the duration period of the substrate structure. | 09-05-2013 |
20130307152 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield. | 11-21-2013 |
20140308780 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield. | 10-16-2014 |
20150303073 | METHOD OF FABRICATING A PACKAGING SUBSTRATE - A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement. | 10-22-2015 |
20150325516 | CORELESS PACKAGING SUBSTRATE, POP STRUCTURE, AND METHODS FOR FABRICATING THE SAME - A method for fabricating a coreless packaging substrate is provided, which includes: forming a dielectric layer on a conductive plate having a plurality of conductive pads; forming a circuit layer on the dielectric layer and forming in the dielectric layer a plurality of conductive vias that electrically connect the circuit layer and the conductive pads; and removing a portion of the conductive plate so as to cause the remaining portion of the conductive plate to form a plurality of conductive elements, thereby dispensing with a core layer and reducing the material and fabrication cost. | 11-12-2015 |
20150333029 | PACKAGE SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A package substrate and a method of fabricating the same are provided. The method includes providing a substrate body having a first surface, a second surface opposing the first surface, a plurality of first electrical connecting pads disposed on the first surface; mounting a metal board on the first electrical connecting pads; and patterning the metal board so as to define a plurality of metal pillars corresponding to the first electrical connecting pads. Therefore, drawbacks of raw edges and unequal heights of the metal pillars can be obviated. | 11-19-2015 |
20150348929 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package structure is provided, which includes: a substrate having opposite top and bottom surfaces and a plurality of conductive pads and a plurality of conductive posts formed therein, wherein the conductive pads are exposed from the bottom surface of the substrate, and the conductive posts are electrically connected to the conductive pads and each of the conductive posts has an end surface exposed from the top surface of the substrate; a plurality of first conductive bumps formed on the end surfaces of the conductive posts; a plurality of second conductive bumps formed on the top surface of the substrate, wherein the second conductive bumps are higher than the first conductive bumps; and at least a first electronic element disposed on and electrically connected to the first conductive bumps, thereby increasing the wiring flexibility and facilitating subsequent disposing of electronic elements without changing existing machines. | 12-03-2015 |
20160071780 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on the carrier an encapsulating layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form in the encapsulating layer via the first surface thereof an opening for an electronic component to be received therein. Before the electronic component is disposed in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, as a defective electronic component is prevented from being disposed in the opening, no defective semiconductor package will be fabricated. | 03-10-2016 |
20160079151 | PACKAGE STRUCTURE WITH AN EMBEDDED ELECTRONIC COMPONENT AND METHOD OF FABRICATING THE PACKAGE STRUCTURE - The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives. | 03-17-2016 |
20160079170 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced. | 03-17-2016 |
20160081186 | SUBSTRATE STRUCTURE AND METHOD OF FABRICATING THE SAME - The present invention provides a substrate structure and a method of fabricating the substrate substrure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulative protection layer, and remvoing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied. | 03-17-2016 |
20160086879 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - A package substrate includes a substrate body having a first surface and a second surface opposite to the first surface; a first circuit layer formed on the first surface and having first conductive pads; a first dielectric layer formed on the first surface and the first circuit; a second circuit layer formed on the first dielectric layer and having second conductive pads; a third circuit layer formed on the second surface and having third conductive pads; a second dielectric layer formed on the second surface and the third circuit layer; a fourth circuit layer formed on the second dielectric layer and having fourth conductive pads; through holes penetrating through the first and second surfaces, and the first and second dielectric layers; and conductive vias penetrating through the through holes and electrically connected to the first, second, third and fourth conductive pads. | 03-24-2016 |
20160093546 | PACKAGE STUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a package structure is provided. The method includes providing a carrier having two opposing surfaces, forming dielectric bodies on the two surfaces of the carrier, respectively, each of the dielectric bodies having a wiring layer embedded therein and a conductive layer formed on the wiring layer, and removing the carrier. Therefore, the wiring layers, the conductive layers and the dielectric bodies are formed on the two surfaces of the carrier, respectively, and the production yield is thus increased. The present invention further provides the package structure thus fabricated. | 03-31-2016 |
Patent application number | Description | Published |
20120131521 | LAYOUT PATTERN - A layout pattern is disclosed. The layout pattern includes: a polygon pattern having at least one segment; and at least one notch formed in the polygon pattern, wherein at least one side of the notch is less than the length of the segment. | 05-24-2012 |
20120319287 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR LAYOUT - A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively. | 12-20-2012 |
20130344043 | METHOD FOR ENHANCING PPARy EXPRESSION - The present invention provides a method for enhancing PPARĪ³ expression, comprising administering a subject in need thereof an effective amount of | 12-26-2013 |
20140045105 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR LAYOUT - A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively. | 02-13-2014 |
20140093814 | METHOD FOR FORMING PHOTOMASKS - A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer. | 04-03-2014 |
20140220482 | METHOD FOR FORMING PATTERNS - A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer. | 08-07-2014 |
20140282295 | Method for Forming Photo-masks and OPC Method - The present invention provides a method for forming at least a photo mask. A first photo-mask pattern relating to a first structure is provides. A second photo-mask pattern relating to a second structure is provides. A third photo-mask pattern relating to a third structure is provides. The first structure, the second structure and the third structure are disposed in a semiconductor structure in sequence. An optical proximity process including a comparison step is provided, wherein the comparison step includes comparing the first photo-mask pattern and the third photo-mask pattern. Last, the first photo-mask pattern is import to form a first mask, the second photo-mask pattern is import to form a second mask, and the third photo-mask pattern is import to form a third mask. The present invention further provides an OPC method. | 09-18-2014 |
20140286926 | METHOD FOR TREATMENT OR PREVENTION OF ALLERGIC DISEASES - The present invention provides a method for reducing an allergic response and treating or preventing an allergic disease, comprising administering a subject in need thereof a therapeutically effective amount of the active ingredient for the treatment or the prevention of allergic diseases, wherein the active ingredient is glyceraldehyde-3-phosphate Dehydrogenase (G3PDH) or the functional variant or fragment thereof. The G3PDH can be isolated from | 09-25-2014 |
20150072272 | Method For Forming Photo-Mask And OPC Method - A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method. | 03-12-2015 |
Patent application number | Description | Published |
20130083189 | SCANNING APPARATUS - A scanning apparatus for scanning a biological sample labeled with fluorochrome includes a case, a sample table, a light source module, an image capture unit, and a driving unit. The light source module provides excitation light to the biological sample on the sample table, in which the fluorochrome is excited to generate fluorescence by fluorescence resonance energy transfer. The image capture unit catches images of the fluorescence from the biological sample. The driving unit is connected to the image capture unit to move the image capture unit. The present invention further includes a filter unit on the image capture unit to filter the fluorescence into the image capture unit. | 04-04-2013 |
20130083190 | DOUBLE-LIGHT CABINET FOR BIOLOGICAL TEST - A double-light cabinet for testing a biological sample labeled with fluorochrome includes a case, in which a light unit and a diffusion unit are received. The light unit has two spot light sources to emit spot lights with specified wavelengths according to the test, and the diffusion unit diffuses the spot lights into surface lights, to which that the biological sample is exposed. The present invention further includes an amber filter unit to filter the surface light to enhance the signal of biological samples. Using the lights with specified wavelengths, the present invention may serve both functions of excitation and illumination of the biological sample. | 04-04-2013 |
20130100660 | MULTIPLE EXCITING LIGHT SYSTEM - A multiple exciting light system for a test of a biological sample labeled with fluorochrome includes a case, in which a sample table, a first light source module, a second light source module, and filter unit are provided. The sample table is provided in the case to put the biological sample thereon. The first light source module is provided in the case to emit visible light as a first light; and the second light source module is provided in the case to emit visible light or invisible light as a second light. The first light from the first light source module and the second light from the second light source module excite the fluorochrome in the biological sample at the same time to generate a third light with a third wavelength by fluorescence resonance superposition energy transfer. | 04-25-2013 |
Patent application number | Description | Published |
20080300816 | ANOMALY DETECTION SYSTEM AND METHOD - An anomaly detection system and a method thereof are disclosed. The system comprises at least a light reflecting unit, a light-emitting unit, an image pick-up unit and a processing module. Each of the light reflecting unit is disposed on an object-to-be-detected that all of which are capable of reflecting light emitted from the light-emitting unit and thus cooperatively generating a reflection image relating to the object-to-be-detected to be received by the image pick-up unit for enabling the same to generate an image signal accordingly. The image signal is then transmitted to the processing module where it is analyzed and compared with a standard image signal so as to determine whether the position of the object-to-be-detected is abnormal. | 12-04-2008 |
20110115638 | METHOD FOR CONTROLLING CLEANING DEVICE - A method for controlling a cleaning device is presented, which includes the following steps. A cleaning device includes a control unit, a fan module, an optical emitter, and an optical sensor. The optical emitter and the optical sensor are located in an air inlet of the fan module. The control unit is preset with a first impedance value (Z1), a second impedance value (Z2), and a threshold, where 005-19-2011 | |
20110225765 | SUCTION CLEANNING MODULE - The present invention provides a suction cleaning module comprising: a first housing, a second housing, a third housing and a fan blower. The second housing, connected to the bottom of the first housing, has a shell section such that a suction channel is formed between the shell section and the first housing and has a dust collection space communicating with the suction channel. The third housing, respectively coupled to the first and second housing, has a filtered flow outlet. The fan blower connected to the third housing has a flow inlet and a flow inlet corresponding to the filtered flow outlet. | 09-22-2011 |
20120110755 | Cleaning Device with Electrostatic Sheet Auto Rolling - A cleaning device with electrostatic sheet auto rolling, comprising: a frame; a power gear set; a roller set, having a first roller, a second roller, a paper feeder roller; and a paper collector roller, arranged axially parallel with each other; and a drive shaft; wherein, the paper feeder roller is coaxially received inside a roller of paper; the first, the second and the paper collector rollers are driven to rotate by the power gear set; the paper collector roller is disposed radial to the paper feeder roller at a side thereof while enabling the first and the second rollers to be arranged therebetween; the drive shaft is enabled to move relative to the frame and perpendicular to the axial direction of the drive shaft; the drive shaft is arranged protruding out of the frame; and the drive shaft, the first and the second rollers are arranged parallel to each other. | 05-10-2012 |
20120111367 | SUCTION CLEANER AND OPERATION METHOD THEREOF - A suction cleaner and an operation method thereof are provided. The suction cleaner includes a housing, a holding part, an impeller module, at least one sensing device, and a controller. An end of the housing has a dust-suction opening. The impeller module is located inside the housing, and a channel is located between the impeller module and the dust-suction opening. The controller is electrically connected to the sensing device to drive and adjust the rotation rate and the suction force of the impeller module, and thus the power consumption of the suction cleaner can be reduced. | 05-10-2012 |
20120210685 | APPARATUS OF CENTRIFUGAL FAN AND A DUST-COLLECTING MODULE USING THE SAME - A centrifugal fan apparatus is disclosed in the present invention. The characteristics of the centrifugal fan apparatus lies in that the width of airflow channel defined between the rim of the impeller and the inner wall of the housing accommodating the impeller is uniform, and two airflow spaces defined between the axial cross section of the impeller and upper housing and lower housing respectively are not symmetry. Due to these two characteristics, the centrifugal fan apparatus is capable of making larger pressure difference to inducing higher flow rate and reducing noise while the centrifugal fan apparatus is operated. The present invention also provides a dust-collecting module that is formed by adopting the centrifugal fan apparatus with a designed dust-collecting casing, which is capable of being a sucker of a vacuum cleaner to collect dust of the surroundings for the purpose of environment cleaning. | 08-23-2012 |
20140129029 | PROXIMITY SENSING METHOD, PROXIMITY SENSING APPARATUS AND MOBILE PLATFORM USING THE SAME - A proximity sensing apparatus is provided. The proximity sensing apparatus includes an encoded signal transmission unit, an interference signal transmission unit and a reception unit. The encoded signal transmission unit transmits an encoded signal, and the interference signal transmission unit transmits an interference signal. The interference signal interferes with the encoded signal to generate an interfered signal. The reception unit receives a sensing signal and outputs the sensing signal to a signal processing unit. The sensing signal is either the interfered signal or the encoded signal. The signal processing unit is electrically connected to the reception unit, and determines whether the sensing signal matches the encoded signal. The signal processing unit further outputs a proximity signal when the sensing signal does not match the encoded signal. | 05-08-2014 |
Patent application number | Description | Published |
20120263215 | TRANSCEIVER CAPABLE OF IQ MISMATCH COMPENSATION ON THE FLY AND METHOD THEREOF - A transceiver capable of IQ mismatch compensation on the fly and a method thereof. The transceiver comprises a transmitter circuit and a loop-back circuit. The transmitter circuit is configured to up-convert a modulation signal on the fly to generate a first RF signal. The loop-back circuit is configured to down-convert the first RF signal and then digitize the down-converted first RF signal to determine a first IQ mismatch parameter based on a first statistical measure of the digitized down-converted RF signal. The transmitter circuit is further configured to compensate for first IQ mismatch in the transmitter circuit according to the first IQ mismatch parameter to generate an IQ compensated modulation signal. | 10-18-2012 |
20130021048 | IC, CIRCUITRY, AND RF BIST SYSTEM - An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment. | 01-24-2013 |
20140154997 | RF TESTING SYSTEM - An integrated circuit (IC) is provided. The IC includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC. | 06-05-2014 |
20150229415 | RF TESTING SYSTEM - An integrated circuit (IC) is provided. The IC includes an RF transmitter configured to generate an RF signal in response to a command signal from test equipment; an RF receiver configured to generate an evaluation signal according to the RF signal, and report the evaluation signal to the test equipment, so that the test equipment performs a test analysis on the evaluation signal to determine a test result, wherein the test equipment is external to the IC. | 08-13-2015 |
20160112148 | LOW-COST TEST/CALIBRATION SYSTEM AND CALIBRATED DEVICE FOR LOW-COST TEST/CALIBRATION SYSTEM - A test/calibration system includes a device under test (DUT) and a calibrated device. The calibrated device is coupled to the DUT, transmits or receives a test signal to or from the DUT in response to a control signal for a test item to test, measure or calibrate functioning or performance of an internal component of the DUT. | 04-21-2016 |
Patent application number | Description | Published |
20120269291 | RF TRANSMITTER, INTEGRATED CIRCUIT DEVICE, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR - A radio frequency (RF) transmitter has at least one digital signal processing module and at least one power amplifier module. The digital signal processing module includes at least one digital pre-distortion component arranged to receive at least one complex input signal, perform two-dimensional non-uniform mapping of the complex input signal to a first, in-phase, digital pre-distortion control word and a further, quadrature, digital pre-distortion control word, and output the in-phase and quadrature pre-distortion digital control words. The power amplifier module includes a first, in-phase, array of switch-mode power cells and at least one further, quadrature, array of switch-mode power cells. The two-dimensional non-uniform mapping has a pre-distortion profile at least partly based on an input/output relationship for the power amplifier module arranged to generate an analogue RF signal based at least partly on the in-phase and quadrature digital pre-distortion control words. | 10-25-2012 |
20120269292 | RF TRANSMITTER, INTEGRATED CIRCUIT DEVICE, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR - A radio frequency (RF) transmitter including at least one digital signal processing module is described. The at least one digital signal processing module is arranged to receive a complex digital input signal, successively apply pre-distortion to the received complex digital input signal with a progressively finer granularity, simultaneously progressively increase a sampling rate of the received complex digital input signal, and output a first, in-phase digital control word and a second, quadrature, digital control word for controlling at least one digital power amplifier component to generate an RF signal representative of the received complex digital input signal. | 10-25-2012 |
20120269293 | RF TRANSMITTER ARCHITECTURE, INTEGRATED CIRCUIT DEVICE, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR - A radio frequency (RF) transmitter architecture includes at least one digital signal processing module. The at least one digital signal processing module is configurable to operate in at least a first mode wherein the at least one digital signal processing module is arranged to receive a digital input signal, select, from a reduced set of digital power amplifier (DPA) control values, a plurality of DPA control values based at least partly on the received digital input signal, perform interpolation of the plurality of selected DPA control values to determine a DPA control value from a non-reduced set of DPA control values representative of the received digital input signal, and output to at least one DPA component the determined DPA control value representative of the received digital input signal. | 10-25-2012 |
20140254720 | PA CELL, PA MODULE, WIRELESS COMMUNICATION UNIT, RF TRANSMITTER ARCHITECTURE AND METHOD THEREFOR - A power amplifier cell includes a first input arranged to receive an in-phase control signal, a second input arranged to receive a quadrature control signal, an input stage arranged to output a drive signal based at least partly on the received in-phase and quadrature control signals, and an output stage arranged to receive at an input thereof the drive signal output by the input stage, and to generate an output signal for the power amplifier cell in response to the received drive signal. | 09-11-2014 |
20140314184 | WIRELESS TRANSMITTER FOR MULTI-MODE CONCURRENT TRANSMISSION OF SIGNALS COMPLYING WITH DIFFERENT COMMUNICATION STANDARDS - A wireless transmitter has a digital baseband module and a radio-frequency (RF) transmitter. The digital baseband module generates a multi-mode modulated signal by using a plurality of digital synthesizers. The RF transmitter has a frequency synthesizer and a digital power amplifier (DPA). The frequency synthesizer generates an oscillation signal with an RF carrier frequency. The DPA generates a multi-standard RF signal according to the multi-mode modulated signal and the oscillation signal. | 10-23-2014 |
20140355717 | RADIO FREQUENCY TRANSMITTER WITH EXTENDED POWER RANGE AND RELATED RADIO FREQUENCY TRANSMISSION METHOD - A radio frequency transmitter includes a digital power amplifier and a bias control circuit. The digital power amplifier is arranged for receiving at least a radio frequency input signal, a digital amplitude control word signal and at least one bias voltage to generate a radio frequency output signal. The bias control circuit is coupled to the digital power amplifier, and is arranged for adjusting the at least one bias voltage according to a power control signal. | 12-04-2014 |
Patent application number | Description | Published |
20120038194 | CHAIR ASSEMBLY - A chair assembly includes a base, a tubular post, a rotary support, and a seat unit. The tubular post extends upwardly from the base and is inclined by an angle of about 45-80 degrees with respect to the base. The rotary support includes a seat support frame, and a rotary shaft extending downwardly from the seat support frame and inserted rotatably into the tubular post. The seat unit includes a looped seat frame mounted on the seat support frame. | 02-16-2012 |
20140346817 | FOLDABLE CHAIR - A foldable chair includes a seat frame unit, a leg frame unit, and a leg frame assembling unit. The leg frame unit includes two leg frames and is pivotable relative to the seat frame unit to change between an unfolded use state and a folded state. The leg frame assembling unit includes at least one resilient fastener and at least one pusher. The resilient fastener has a locking head to immobilize the one of the leg frames in the unfolded use state. The pusher has a protruding portion to push the locking head that is retracted inwardly from the seat frame unit, thereby releasing the one of the leg frames from the unfolded use state relative to the seat frame unit. | 11-27-2014 |
20160073783 | SEAT-FORMING ASSEMBLY AND A CHAIR HAVING THE SAME - A chair includes a frame having a coupling member, and a seat-forming assembly. The seat-forming assembly includes first and second plate members, a linking member and a hook unit. The first and second plate members serve respectively as a seat and a backrest of the chair, and each have a connecting portion and a hook-mounting portion opposite to each other. The linking member links the connecting portions of the first and second plate members together. The hook unit includes a plurality of first hooks connected to the hook-mounting portion of the first plate member, and a plurality of second hooks connected to the hook-mounting portion of the second plate member. The first and second hooks are capable of detachably engaging the coupling member. | 03-17-2016 |