Patent application number | Description | Published |
20080266402 | METHOD AND DEVICES FOR LINKING AUDIOVISUAL CAPTURE DEVICE - A method and devices for linking an audiovisual capture device, which enable an operator to use a terminal device at his end to locate an audiovisual capture device installed at another end through a network architecture, thereby facilitating the Implementation of the subsequent installation and setting operations. The method includes: execution of a first processing procedure by the audiovisual capture device, and execution of a second processing procedure by the terminal device. After the two processing procedures have been completed, the information linking is effected between the terminal device and the audiovisual capture device, which enables the operator to use the terminal device to execute installation and setting up of the audiovisual capture device. | 10-30-2008 |
20080279164 | METHOD FOR CONNECTING TO A WIRELESS NETWORK - The present invention provides a method for connecting with a wireless network device. The method includes following steps: upon configuring the wireless network device, executing a first target procedure to connect the wireless network device with the terminal device; executing a second target procedure, allowing the sharing device to be searched by the wireless network device according to at least one target signal; executing a third target procedure to select a target sharing device corresponding to the wireless network device according to the target signal; and connecting wirelessly the wireless network device with the target sharing device. | 11-13-2008 |
20080285484 | METHOD FOR ANALYZING A NETWORK ENVIRONMENT - A method for analyzing a network environment, in which the method comprises the following steps: Acquiring a plurality of connection data of all network cards of a terminal device; according to connection data, determining whether or not a terminal device uses a PPPoEconnection is used to connect to a network system; determining whether or not an IP address of the terminal device is a public IP address and determining whether or not the terminal device uses DHCP to acquire a target IP address. | 11-20-2008 |
Patent application number | Description | Published |
20130293993 | OUTPUT CIRCUITS WITH ELECTROSTATIC DISCHARGE PROTECTION - An output circuit is provided and includes first and second output stage elements, a detection circuit, a control circuit, and a first pre-driver. The first and second output stage elements are coupled in series between a power terminal and the ground terminal. The detection circuit detect whether an electrostatic discharge event occurs at an output terminal between the two output stage elements to generate a control signal. The control circuit controls a state of the first output stage element when the control circuit is enabled according to the control signal. The first pre-driver controls the state of the first output stage element when the first per-driver is enabled according to the control signal. When the detection circuit detects that the electrostatic discharge event occurs at the output terminal, the control circuit is enabled to turn on the first output stage element, and the first pre-driver is disabled. | 11-07-2013 |
20150262994 | SURGE-PROTECTION CIRCUIT AND SURGE-PROTECTION METHOD - A surge-protection circuit for a chip is provided. The surge-protection circuit includes a detection element and a protection element. The detection element is embedded on the chip and arranged between a first terminal and a second terminal, and the detection element is utilized to detect whether an abrupt voltage variation occurs due to a surge or not and generate an enabling signal when the abrupt voltage variation occurs. The protection element is embedded on the chip and coupled to the detection element, and the protection element is utilized to adjust and reduce the abrupt voltage variation through bypassing high energy generated by the surge after receiving the enabling signal. | 09-17-2015 |
20150340359 | SIGNAL RECEIVING CIRCUIT AND SIGNAL TRANSCEIVING CIRCUIT - A signal transceiving circuit comprising an IC including a signal transmitting part. The signal transmitting part comprises: a first I/O pad; a second I/O pad; a first output stage circuit, coupled to the first I/O pad; a second output stage circuit, coupled to the second I/O pad; and a first surge protecting device, comprising a first terminal coupled to the first output stage circuit and the first I/O pad, and comprising a second terminal coupled to the second output stage circuit and the second I/O pad. | 11-26-2015 |
Patent application number | Description | Published |
20090310388 | METHOD AND APPARATUS FOR MEASURING THE SWITCHING CURRENT OF POWER CONVERTER OPERATED AT CONTINUOUS CURRENT MODE - An apparatus for detecting a switching current of the power converter, wherein the apparatus includes a signal generation circuit, a sample-and-hold circuit, and a calculating circuit. The signal generation circuit generates a sample signal in accordance with the pulse width of a switching signal. The sample-and-hold circuit is coupled to receive the sample signal and switching current signal for generating a first current signal and a second current signal. The calculating circuit is coupled to receive the first current signal and the second current signal for generating output signals. The switching signal is used for switching the magnetic device of the power converter, and the switching current signal is correlated to the switching current of the power converter; the output signals are correlated to the value of the switching current of the power converter. | 12-17-2009 |
20100090758 | LOW-PASS FILTER - A low-pass filter of the present invention comprises a plurality of filter units and a regulation unit. The filter units are coupled in series with each other and receive an input signal to filter the input signal for generating an output signal. The regulation unit is coupled to the filter units to regulate voltage levels of the filter units. The low-pass filter of the present invention can be integrated within the integrated circuit and reduce the prime cost. | 04-15-2010 |
20110255309 | High-Speed Reflected Signal Detection for Primary-Side Controlled Power Converters - A controller for a power converter includes a clamping circuit, a switching circuit and a pulse generator. The clamping circuit is coupled to an input terminal of the controller for detecting a detection signal from a transformer. The switching circuit generates a switching signal to switch the transformer in response to the detection signal for regulating the power converter. A maximum level of the detection signal is clamped to be under a level of a threshold voltage during an off-period of the switching signal. Since the maximum level of the detection signal is clamped and the oscillating energy of the reflected signal is discharged, the speed of detecting the detection signal is increased. Therefore, the regulation of the primary-side controlled power converter can be improved accordingly. | 10-20-2011 |
Patent application number | Description | Published |
20130250523 | HEAT DISSIPATING ASSEMBLY AND ELASTIC FASTENING MEMBER THEREOF - A heat dissipating assembly which releases heat produced by an electronic device comprising a heat dissipating device and a plurality of elastic fastening members. The heat dissipating assembly includes a base plate having a plurality of engaging holes formed thereon. Each elastic fastening member includes a connecting member and a spring. The connecting member has a head portion and a bolt body that extends therefrom. The bolt body has an outer thread formed on the surface thereof and is being insertable into the respective engaging hole. The spring includes a winding portion woundable around the outer periphery of the bolt body, a clutching portion outwardly extended and downwardly bent from the bottom end of the winding portion to the base surface of the base plate, and a fastening segment extending from the clutching portion back under the winding portion. The instant disclosure further provides an elastic fastening member. | 09-26-2013 |
20130258584 | COMPUTER SYSTEM - A computer system is provided. The computer system includes a housing, a mainboard, a first heat source, a second heat source and a flow field modulator. An inlet and an outlet are formed on the housing. The mainboard is disposed in the housing. The first heat source is located on a first location of the mainboard. The second heat source is located on a second location of the mainboard. The flow field modulator is disposed on the mainboard including a control unit, a piezoelectric element and a guiding sheet. The control unit is electrically connected to the mainboard. The piezoelectric element is electrically connected to the control unit. The guiding sheet is connected to the piezoelectric element. | 10-03-2013 |
20140179134 | PROTECTIVE COVER MECHANISM FOR PROTECTING A SOCKET OF AN ELECTRONIC DEVICE AND ELECTRONIC DEVICE THEREWITH - The present invention discloses a protective cover mechanism for protecting a socket of an electronic device. The protective cover mechanism includes a base and a fluid restrictor. The base is disposed on the socket for covering the socket. The fluid restrictor is installed on the base and is for blocking airflow on a side of the socket, so as to guide the airflow to a neighboring electronic component. | 06-26-2014 |
Patent application number | Description | Published |
20110003420 | Fabrication method of gallium nitride-based compound semiconductor - The present invention discloses a method for fabricating gallium nitride(GaN)-based compound semiconductors. Particularly, this invention relates to a method of forming a transition layer on a zinc oxide (ZnO)-based semiconductor layer by the steps of forming a wetting layer and making the wetting layer nitridation. The method not only provides a function of protecting the ZnO-based semiconductor layer, but also uses the transition layer as a buffer layer for a following epitaxial growth of a GaN-based semiconductor layer, and thus, the invention may improve the crystal quality of the GaN-based semiconductor layer effectively. | 01-06-2011 |
20150228731 | MODIFIED CHANNEL POSITION TO SUPPRESS HOT CARRIER INJECTION IN FINFETS - Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode. | 08-13-2015 |
20150263122 | AIR-GAP OFFSET SPACER IN FINFET STRUCTURE - The present disclosure relates to a method of forming a FinFET device having sidewalls spacers comprising an air gap that provides for a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a fin of semiconductor material on a semiconductor substrate. A gate structure, having a gate dielectric layer and an overlying gate material layer, is formed at a position overlying the fin of semiconductor material. Sidewall spacers are formed at positions abutting opposing sides of the gate structure. Respective sidewall spacers have a first layer of insulating material abutting the gate structure and a second layer of insulating material separated from the first layer of insulating material by an air gap. By forming the FinFET device to have sidewall spacers with air gaps, the parasitic capacitance of the FinFET device and a corresponding RC time delay are decreased. | 09-17-2015 |
20150279975 | FIN SIDEWALL REMOVAL TO ENLARGE EPITAXIAL SOURCE/DRAIN VOLUME - A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface. | 10-01-2015 |
20160035726 | FIN SIDEWALL REMOVAL TO ENLARGE EPITAXIAL SOURCE/DRAIN VOLUME - A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface. | 02-04-2016 |