Patent application number | Description | Published |
20140189399 | METHODS, SYSTEMS AND APPARATUS TO MANAGE POWER CONSUMPTION OF A GRAPHICS ENGINE - Methods and apparatus are disclosed to manage power consumption at a graphics engine. An example method to manage power usage of a graphics engine via an application level interface includes obtaining a policy directive for the graphics engine via the application level interface, the policy directive identifying a threshold corresponding to power consumed by the graphics engine operating in a first graphics state. The example method also includes determining a power consumed by the graphics engine during operation. The example method also includes comparing the power consumed to the threshold of the policy directive, and when the threshold is met, setting the graphics engine in a second graphics state to cause the graphics engine to comply with the policy directive. | 07-03-2014 |
20140281637 | MEMORY STATE MANAGEMENT FOR ELECTRONIC DEVICE - In one embodiment a controller comprises logic to determine whether an electronic device is operating in a low power state and in response to a determination that the electronic device is operating in a low power state, implement a memory state management routine which reduces power to at least a section of volatile memory in the memory system. Other embodiments may be described. | 09-18-2014 |
20150095600 | ATOMIC TRANSACTIONS TO NON-VOLATILE MEMORY - Durable atomic transactions for non-volatile media are described. A processor includes an interface to a non-volatile storage medium and a functional unit to perform instructions associated with an atomic transaction. The instructions are to update data at a set of addresses in the non-volatile storage medium atomically. The functional unit is operable to perform a first instruction to create the atomic transaction that declares a size of the data to be updated atomically. The functional unit is also operable to perform a second instruction to start execution of the atomic transaction. The functional unit is further operable to perform a third instruction to commit the atomic transaction to the set of addresses in the non-volatile storage medium, wherein the updated data is not visible to other functional units of the processing device until the atomic transaction is complete. | 04-02-2015 |
20150317764 | METHODS, SYSTEMS AND APPARATUS TO MANAGE POWER CONSUMPTION OF A GRAPHICS ENGINE - Methods and apparatus are disclosed to manage power consumption at a graphics engine. An example method to manage power usage of a graphics engine via an application level interface includes obtaining a policy directive for the graphics engine via the application level interface, the policy directive identifying a threshold corresponding to power consumed by the graphics engine operating in a first graphics state. The example method also includes determining a power consumed by the graphics engine during operation. The example method also includes comparing the power consumed to the threshold of the policy directive, and when the threshold is met, setting the graphics engine in a second graphics state to cause the graphics engine to comply with the policy directive. | 11-05-2015 |
Patent application number | Description | Published |
20130166358 | DETERMINING A LIKELIHOOD THAT EMPLOYMENT OF AN EMPLOYEE WILL END - Techniques for determining whether employment of an employee will end, such as determining a risk of attrition for an employee. In some embodiments, one or more types of employment information for an employee may be evaluated and weighted to determine a likelihood that employment of the employee will end. Types of employment information that may be evaluated may include interaction information relating to a manner in which an employee interacts with coworkers, including a manner in which an employee is detected to use one or more software tools to interact with coworkers. Types of employment information that may be evaluated may include performance information, which may include performance ratings of an employee and information regarding an employee's capability to perform in the position. Types of employment information may include career path information, which may include employment history information for an employee and/or market information indicating job opportunities in the industry. | 06-27-2013 |
20130346501 | System and Method for Calculating Global Reputation - As social networks become more powerful and sophisticated, each member of a social network may belong to different communities. The computing reputation for users in a single community is not adequate anymore. As a result, a method of calculating global reputation for each member is desirable. Various considerations are described to address challenges related to global reputation for a user who participates in activities among multiple communities. Considerations on accessibility of a community, quality vs. quantity of submissions, posting ideas vs. comments, weighting of each community, and volatility of the reputation value are discussed in the present invention. Finally, a formula for calculating a global reputation value of the user is proposed by combining all the considerations. A system that implements the global reputation computation is described. | 12-26-2013 |
Patent application number | Description | Published |
20100076941 | MATRIX-BASED SCANS ON PARALLEL PROCESSORS - A system and method for performing a scan of an input sequence in a parallel processor having a shared register file. A two dimensional matrix is generated, having a number of rows representing a number of threads and a number of columns based on the input sequence block size and the number of rows. One or more padding columns may be added to the matrix to avoid or reduce memory bank conflicts. A first traversal of the rows performs a reduction or a scan of each of the rows in parallel, storing the reduction values. The reduction values are used during a second traversal to propagate the reduction values. In a segmented scan, propagation is selectively performed based on flags representing segment boundaries. | 03-25-2010 |
20120311573 | ISOLATION OF VIRTUAL MACHINE I/O IN MULTI-DISK HOSTS - Embodiments of the present invention relate to systems, methods, and computer storage media for concurrently maintaining a spanned virtual hard drive across two or more computer-storage media and a non-spanned virtual hard drive on one of computer-storage media. The method includes storing data of the spanned virtual hard drive across the computer-storage media utilizing volume spanning. While the spanned virtual hard drive is maintained on the computer storage media, the method includes storing data of the non-spanned virtual hard drive on one of the computer-storage media. | 12-06-2012 |
20150268980 | ISOLATION OF VIRTUAL MACHINE I/O IN MULTI-DISK HOSTS - Embodiments of the present invention relate to systems, methods, and computer storage media for concurrently maintaining a spanned virtual hard drive across two or more computer-storage media and a non-spanned virtual hard drive on one of computer-storage media. The method includes storing data of the spanned virtual hard drive across the computer-storage media utilizing volume spanning. While the spanned virtual hard drive is maintained on the computer storage media, the method includes storing data of the non-spanned virtual hard drive on one of the computer-storage media. | 09-24-2015 |
Patent application number | Description | Published |
20090102843 | IMAGE-BASED PROXY ACCUMULATION FOR REALTIME SOFT GLOBAL ILLUMINATION - General and realtime technique for soft global illumination in low-frequency environmental lighting. The technique accumulates over a relatively few spherical proxies that approximate the light blocking and re-radiating effect of dynamic geometry. Soft shadows are computed by accumulating log visibility vectors for each sphere proxy as seen by each receiver point. Inter-reflections are computed by accumulating vectors representing the proxy's unshadowed radiance when illuminated by the environment. Both vectors capture low-frequency directional dependence using the spherical harmonic basis. Additionally, a new proxy accumulation method splats each proxy to receiver pixels in image space to collect the proxy's contribution to shadowing and indirect lighting. A soft rendering pipeline unifies direct and indirect soft effects with an accumulation methodology that maps entirely to a graphics processing unit and outperforms previous vertex-based methods. | 04-23-2009 |
20100088356 | FAST COMPUTATION OF GENERAL FOURIER TRANSFORMS ON GRAPHICS PROCESSING UNITS - Described is a technology for use with general discrete Fourier transforms (DFTs) performed on a graphics processing unit (GPU). The technology is implemented in a general library accessed through GPU-independent APIs. The library handles complex and real data of any size, including for non-power-of-two data sizes. In one implementation, the radix-2 Stockham formulation of the fast Fourier transform (FFT) is used to avoid computationally expensive bit reversals. For non-power of two data sizes, a Bluestein z-chirp algorithm may be used. | 04-08-2010 |
20100106758 | COMPUTING DISCRETE FOURIER TRANSFORMS - A system described herein includes a selector component that receives input data that is desirably transformed by way of a Discrete Fourier Transform, wherein the selector component selects one of a plurality of algorithms for computing the Discrete Fourier Transform from a library based at least in part upon a size of the input function. An evaluator component executes the selected one of the plurality of algorithms to compute the Discrete Fourier Transform, wherein the evaluator component causes leverages shared memory of a processor to compute the Discrete Fourier Transform. | 04-29-2010 |
20110081023 | REAL-TIME SOUND PROPAGATION FOR DYNAMIC SOURCES - Described herein are techniques pertaining to real-time propagation of an arbitrary audio signal in a fixed virtual environment with dynamic audio sources and receivers. A wave-based numerical simulator is configured to compute response signals in the virtual environment with respect to a sample signal at various source and receiver locations. The response signals are compressed and placed in the frequency domain to generate frequency responses. Such frequency responses are selectively convolved with the arbitrary audio signal to allow real-time propagation with moving sources and receivers in the virtual environment. | 04-07-2011 |
20110251829 | SIMULATING PAINTING - A paint simulation system described herein includes a brush component that outputs a three-dimensional computer-implemented model of an image editing tool. A paint component receives the three-dimensional computer-implemented model and generates a two-dimensional map corresponding to a footprint of the three-dimensional model with respect to a computer-implemented canvas, wherein resolution of the two-dimensional map is substantially similar to resolution of a paint map of the computer-implemented canvas. | 10-13-2011 |
Patent application number | Description | Published |
20080242117 | APPARATUS TO REDUCE WAFER EDGE TEMPERATURE AND BREAKAGE OF WAFERS - In some embodiments radiation incident on a wafer is provided to perform an annealing process, and the wafer is cooled at an edge portion to reduce temperature and stress on the wafer. Other embodiments are described and claimed. | 10-02-2008 |
20090323759 | Temperature measurement with reduced extraneous infrared in a processing chamber - Temperature measurement using a pyrometer in a processing chamber is described. The extraneous light received by the pyrometer is reduced. In one example, a photodetector is used to measure the intensity of light within the processing chamber at a defined wavelength. A temperature circuit is used to convert the measured light intensity to a temperature signal, and a doped optical window between a heat source and a workpiece inside processing chamber is used to absorb light at the defined wavelength directed at the workpiece from the heat source. | 12-31-2009 |
20090325392 | SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES - An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described. | 12-31-2009 |
20150179469 | METHOD AND SYSTEM TO CONTROL POLISH RATE VARIATION INTRODUCED BY DEVICE DENSITY DIFFERENCES - An embodiment includes forming a first film over first and second portions of a SOC, the first portion including a first density of structures and the second portion including a second density of structures with the first density being denser than the second density; forming a second film over the first film; polishing the second film to remove some of the second film and form (a) a first section of the second film between sections of the first film located over the first portion, and (b) a second section of the second film between sections of the second film located over the second portion; etching the first film over the first and second portions and etching the first and second sections of the second film; and polishing the first film to expose top surfaces of the structures of the first and second portions. Other embodiments are described herein. | 06-25-2015 |
20150179567 | USING MATERIALS WITH DIFFERENT ETCH RATES TO FILL TRENCHES IN SEMICONDUCTOR DEVICES - An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; a first atomic layer deposition (ALD) layer on the conductive region and the opening sidewalls; a second ALD layer on a portion of the first ALD layer, and a third ALD layer within the opening and on the first ALD layer. Other embodiments are described herein. | 06-25-2015 |
20150179785 | TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS - Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed. | 06-25-2015 |