Patent application number | Description | Published |
20090042934 | Sulfonyl-Quinoline Derivatives - The present invention relates to new mGluR1 and mGluR5 receptor subtype preferring ligands of formula (I) and/or salts and/or hydrates and/or solvates and/or polymorphs thereof. The invention also relates to processes and intermediates for their preparation, to pharmaceutical compositions containing these compounds and to their use in treatment and/or prevention of conditions which require modulation of mGluR1 and mGluR5 receptors. | 02-12-2009 |
20090149495 | COMPOUNDS - The present invention relates to new mGluR1 and mGluR5 receptor subtype preferring ligands of formula (I) wherein X represents a group selected from CO, SO, SO | 06-11-2009 |
20090270371 | QUINOLINE DERIVATIVES USEFUL IN THE TREATMENT OF MGLUR5 RECEPTOR-MEDIATED DISORDERS - Compounds of formula (I): and/or enantiomers and/or racemates and/or diastereomers and/or pharmaceutically acceptable salts thereof formed with acids or bases, to the process for their preparation, to the intermediates of the preparation process, to the pharmaceutical formulations containing these compounds and to their use in the prevention and/or treatment of mGluR5 receptor-mediated disorders. | 10-29-2009 |
20090326001 | THIENOPYRIDINE DERIVATIVES AS MODULATORS OF METABOTROPIC GLUTAMATE RECEPTORS - The present invention relates to new mGluR1 and niGluR5 receptor subtype preferring ligands of formula (I): wherein X represents a group selected from (CH | 12-31-2009 |
20090326002 | Thieno [2,3-b] Pyridine Compounds with mGluR Activity - Provided herein are Thieno[2,3-b]pyridine compounds with mGluR activity. Also provided herein are processes and intermediates for the preparation of the Thieno[2,3-b]pyridine compounds, pharmaceutical compositions containing these compounds, and the use of these compounds in treatment, therapy, and/or prevention of conditions which require modulation of mGluR1 and mGluR5 receptors. | 12-31-2009 |
20100022521 | COMPOUNDS - The present invention relates to new mGluR1 and mGluR5 receptor subtype preferring ligands of formula (I) wherein X represents a group selected from SO, SO2; Y represents a group selected from (CH | 01-28-2010 |
20110184014 | NEW COMPOUNDS - The present invention relates to new mGluR1 and mGluR5 receptor subtype preferring ligands of formula (I); wherein Y represents a substituent selected from hydrogen, methyl, fluoro, chloro, bromo, methoxy; Z is hydrogen or methyl; R is an optionally substituted heteroaryl, and/or salts and/or hydrates and/or solvates thereof, to the processes for producing the same, to pharmaceutical compositions containing the same and to their use in therapy and/or prevention of pathological conditions which require the modulation of mGluR1 and mGluR5 receptors such as neurological disorders, psychiatric disorders, acute and chronic pain and neuromuscular dysfunctions of the lower urinary tract. | 07-28-2011 |
Patent application number | Description | Published |
20080229193 | PROGRAM PRODUCT SUPPORTING SPECIFICATION OF SIGNALS FOR SIMULATION RESULT VIEWING - According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of said multiple signals are then included within a presentation of simulation results. | 09-18-2008 |
20080294413 | PROGRAM PRODUCT SUPPORTING PHASE EVENTS IN A SIMULATION MODEL OF A DIGITAL SYSTEM - According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase. | 11-27-2008 |
20100153083 | SELECTIVE COMPILATION OF A SIMULATION MODEL IN VIEW OF UNAVAILABLE HIGHER LEVEL SIGNALS - In response to receiving HDL file(s) that specify a plurality of hierarchically arranged design entities defining a design to be simulated and that specify an instrumentation entity for monitoring simulated operation of the design, an instrumented simulation executable model of the design is built. Building the model includes compiling the HDL file(s) specifying the plurality of hierarchically arranged design entities defining the design and instantiating at least one instance of each of the plurality of hierarchically arranged design entities, and further includes instantiating an instance of the instrumentation entity within an instance of a particular design entity among the plurality of design entities and, based upon a reference in an instrumentation statement in the one or more HDL files, logically attaching an input of the instance of the instrumentation entity to an input source within the design that is outside the scope of the particular design entity. | 06-17-2010 |
20100223584 | Logic Design Verification Techniques for Liveness Checking With Retiming - A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned. | 09-02-2010 |
20120192133 | LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING - A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned. | 07-26-2012 |
20130275930 | SYNTHESIZING VHDL MULTIPLE WAIT FSMS INTO RT LEVEL FSMS BY PREPROCESSING - Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer. | 10-17-2013 |