Patent application number | Description | Published |
20080224221 | CASCODE CURRENT MIRROR AND METHOD - A cascode amplifier (CA) ( | 09-18-2008 |
20080224237 | SEMICONDUCTOR DEVICES - An embodiment of a semiconductor device includes a gate electrode overlying a substrate and a lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms a gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain. | 09-18-2008 |
20090244928 | DUAL GATE LATERAL DIFFUSED MOS TRANSISTOR - A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions. | 10-01-2009 |
20090315145 | ADJUSTABLE BIPOLAR TRANSISTORS FORMED USING A CMOS PROCESS - By providing a novel bipolar device design implementation, a standard CMOS process ( | 12-24-2009 |
20100025765 | DUAL GATE LDMOS DEVICES - An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg | 02-04-2010 |
20100156388 | CASCODE CURRENT MIRROR AND METHOD - Embodiments of a cascode amplifier (CA) include a bottom transistor with a relatively thin gate dielectric and higher ratio of channel length to width and a series coupled top transistor with a relatively thick gate dielectric and a lower ratio of channel length to width. A cascode current mirror (CCM) is formed using a coupled pair of CAs, one forming the reference current (RC) side and the other forming the mirror current side of the CCM. The gates of the bottom transistors are tied together and to the common node between the series coupled bottom and top transistors of the RC side, and the gates of the top transistors are coupled together and to the top drain node of the RC side. The area of the CCM can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage. | 06-24-2010 |
20110089500 | MULTI-GATE SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate, a source region formed over the substrate, a drain region formed over the substrate, a first gate electrode over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode over the substrate adjacent to the drain region and between the source and drain regions. | 04-21-2011 |
20110147893 | BIPOLAR TRANSISTORS WITH HUMP REGIONS - By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required. | 06-23-2011 |
20110169078 | SWITCH MODE CONVERTER EMPLOYING DUAL GATE MOS TRANSISTOR - A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions. | 07-14-2011 |
20110260247 | LDMOS TRANSISTORS WITH A SPLIT GATE - A transistor including a source region, drain region, channel region, drift region, isolation region, a first gate structure over the channel region, and a second gate structure over the isolation region is provided. The drift region includes a first portion located under the isolation region and a second portion located laterally adjacent to the isolation region. The first gate structure is separated by a first separation space from the second gate structure. The first separation space is located over a portion of the second portion of the drift region and a portion of the isolation region. | 10-27-2011 |
20120043608 | Partially Depleted Dielectric Resurf LDMOS - An partially depleted Dieler LDMOSFET transistor ( | 02-23-2012 |
20120098095 | BIPOLAR TRANSISTOR WITH IMPROVED STABILITY - Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface. | 04-26-2012 |
20120205738 | NEAR ZERO CHANNEL LENGTH FIELD DRIFT LDMOS - Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space ( | 08-16-2012 |
20130134511 | Semiconductor Device with Self-Biased Isolation - A device includes a semiconductor substrate including a surface, a drain region in the semiconductor substrate having a first conductivity type, a well region in the semiconductor substrate on which the drain region is disposed, the well region having the first conductivity type, a buried isolation layer in the semiconductor substrate extending across the well region, the buried isolation layer having the first conductivity type, a reduced surface field (RESURF) region disposed between the well region and the buried isolation layer, the RESURF region having a second conductivity type, and a plug region in the semiconductor substrate extending from the surface of the substrate to the RESURF region, the plug region having the second conductivity type. | 05-30-2013 |
20130234246 | Semiconductor Device with Composite Drift Region - A device includes a semiconductor substrate, a channel region in the semiconductor substrate having a first conductivity type, and a composite drift region in the semiconductor substrate, having a second conductivity type. The composite drift region includes a first drift region and a second drift region spaced from the channel region by the first drift region. The device further includes a drain region in the semiconductor substrate, spaced from the channel region by the composite drain region, and having the second conductivity type. The first drift region has a dopant concentration profile with a first concentration level where adjacent the channel region and a second concentration level where adjacent the second drift region, the first concentration level being higher than the second concentration level. In some embodiments, the first and second drift regions are stacked vertically, with the first drift region being shallower than the second drift region. | 09-12-2013 |
20130292764 | Semiconductor Device with Drain-End Drift Diminution - A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction. | 11-07-2013 |
20130344672 | SEMICONDUCTOR DEVICE WITH SELF-BIASED ISOLATION - A method of fabricating a reduced surface field (RESURF) transistor includes forming a first well in a substrate, the first well having a first conductivity type, doping a RESURF region of the first well to have a second conductivity type, doping a portion of the first well to form a drain region of the RESURF transistor, the drain region having the first conductivity type, and forming a second well in the substrate, the second well having the second conductivity type. A plug region is formed in the substrate, the plug region extending to the RESURF region. | 12-26-2013 |
20140001545 | HIGH BREAKDOWN VOLTAGE LDMOS DEVICE | 01-02-2014 |
20140027849 | LDMOS DEVICE AND METHOD FOR IMPROVED SOA - A lateral-diffused-metal-oxide-semiconductor device having improved safe-operating-area is provided. The LDMOS device includes spaced-apart source and drain, separated by a first insulated gate structure, and spaced-apart source and body contact The spaced-apart source and BC are part of the emitter-base circuit of a parasitic bipolar transistor that can turn on prematurely, thereby degrading the SOA of prior art four-terminal LDMOS devices. Rather than separating the source and BC with a shallow-trench-isolation region as in the prior art, the semiconductor surface in the gap between the spaced-apart source and BC has there-over a second insulated gate structure, with its gate conductor electrically tied to the BC. When biased, the second insulated gate structure couples the source and BC lowering the parasitic resistance in the emitter-base circuit, thereby delaying turn-on of the parasitic transistor and improving the SOA of such 4-T LDMOS devices. | 01-30-2014 |
20140054694 | Semiconductor Device with HCI Protection Region - A device includes a semiconductor substrate, a drift region in the semiconductor substrate and having a first conductivity type, an isolation region within the drift region, and around which charge carriers drift on a path through the drift region during operation, and a protection region adjacent the isolation region in the semiconductor substrate, having a second conductivity type, and disposed along a surface of the semiconductor substrate. | 02-27-2014 |
20140070311 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region. | 03-13-2014 |
20140070312 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second vertical drift region of semiconductor material, and a buried lateral drift region of semiconductor material that abuts the vertical drift regions. In one or more embodiments, the vertical drift regions and buried lateral drift region have the same conductivity type, wherein a body region of the opposite conductivity type overlies the buried lateral drift region between the vertical drift regions. | 03-13-2014 |
20140110814 | Resurf High Voltage Diode - A trench-isolated RESURF diode structure ( | 04-24-2014 |
20140110815 | High Voltage Diode - A trench-isolated RESURF diode structure ( | 04-24-2014 |
20140134820 | METHODS FOR PRODUCING BIPOLAR TRANSISTORS WITH IMPROVED STABILITY - Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface. | 05-15-2014 |
20140203358 | SEMICONDUCTOR DEVICE WITH ENHANCED 3D RESURF - A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region. | 07-24-2014 |
20140203410 | DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS - Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer. | 07-24-2014 |
20140206168 | METHODS FOR PRODUCING NEAR ZERO CHANNEL LENGTH FIELD DRIFT LDMOS - Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space adjacent the drain, is avoided by providing a lightly doped region of a first conductivity type (CT) separating the first CT drift space from an opposite CT WELL region in which the first CT source is located, and a further region of the opposite CT (e.g., formed by an angled implant) extending through part of the WELL region under an edge of the gate located near a boundary of the WELL region into the lightly doped region, and a shallow still further region of the first CT Ohmically coupled to the source and ending near the gate edge whereby the effective channel length in the further region is reduced to near zero. Substantial improvement in BVDSS and/or Rdson can be obtained without degrading the other or significant adverse affect on other device properties. | 07-24-2014 |
20140209988 | NONVOLATILE MEMORY BITCELL - A multiple time programmable nonvolatile memory device having a single polysilicon memory cell includes a select transistor and a bitcell transistor. The bitcell transistor has asymmetrically configured source, drain, and channel regions including asymmetrically configured source-body and drain-body junctions. Compared with the drain-body junction, the impurity concentration gradient of the source-body junction is more gradual, which may significantly improve program disturb immunity. The bitcell transistor gate may be connected to an electrode of a coupling capacitor, but may be otherwise floating or Ohmically isolated. The floating gate of the bitcell is protected by a dielectric layer for potentially improved data retention. | 07-31-2014 |
20140235025 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second vertical drift region of semiconductor material, and a buried lateral drift region of semiconductor material that abuts the vertical drift regions. In one or more embodiments, the vertical drift regions and buried lateral drift region have the same conductivity type, wherein a body region of the opposite conductivity type overlies the buried lateral drift region between the vertical drift regions. | 08-21-2014 |
20140332901 | SEMICONDUCTOR DEVICE WITH NOTCHED GATE - A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, a drain region disposed in the semiconductor substrate, having the second conductivity type, and spaced from the source region to define a conduction path, a gate structure supported by the semiconductor substrate, configured to control formation of a channel in the conduction path during operation, and having a side adjacent the source region that comprises a notch, the notch defining a notch area, and a notch region disposed in the semiconductor substrate in the notch area and having the first conductivity type. | 11-13-2014 |
20150056751 | DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS - Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer. | 02-26-2015 |
20150097238 | Mergeable Semiconductor Device with Improved Reliability - A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure. | 04-09-2015 |
20150123236 | Diodes with Multiple Junctions and Fabrication Methods Therefor - An embodiment of a diode includes a semiconductor substrate, a first contact region having a first conductivity type, a second contact region laterally spaced from the first contact region, and having a second conductivity type, an intermediate region disposed in the semiconductor substrate between the first and second contact regions, electrically connected with the first contact region, and having the first conductivity type, and a buried region disposed in the semiconductor substrate, having the second conductivity type, and electrically connected with the second contact region. The buried region extends laterally across the first contact region and the intermediate region to establish first and second junctions, respectively. The first junction has a lower breakdown voltage than the second junction. | 05-07-2015 |
20150155350 | Resurf High Voltage Diode - A trench-isolated RESURF diode structure ( | 06-04-2015 |
20150228713 | High Voltage Diode - A trench-isolated RESURF diode structure ( | 08-13-2015 |
20150270333 | Semiconductor Device with Peripheral Breakdown Protection - A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type. | 09-24-2015 |
20150325565 | Composite Semiconductor Device with Multiple Threshold Voltages - A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor. | 11-12-2015 |
20150325674 | Methods of Fabricating Diodes with Multiple Junctions - An embodiment of a method of fabricating a diode having a plurality of regions of a first conductivity type and a buried region of a second conductivity type includes performing a first dopant implantation procedure to form the buried region, performing a second dopant implantation procedure to form an intermediate region of the plurality of regions, and performing a third dopant implantation procedure to form a contact region of the plurality of regions. The second and third dopant implantation procedures are configured such that the intermediate region is electrically connected with the contact region. The first, second, and third dopant implantation procedures are configured such that the buried region extends laterally across the contact region and the intermediate region to establish first and second junctions of the diode, respectively, and such that the first junction has a lower breakdown voltage than the second junction. | 11-12-2015 |
20150333177 | SEMICONDUCTOR DEVICE WITH COMPOSITE DRIFT REGION AND RELATED FABRICATION METHOD - A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section. | 11-19-2015 |
20150364576 | RELIABILITY IN MERGEABLE SEMICONDUCTOR DEVICES - A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region. | 12-17-2015 |
Patent application number | Description | Published |
20100221726 | RELATING TO DEVICES - A method of analysis, instrument for analysis and device for use in such an instrument are provided, which perform a number of processes need to reach a useful result in the context of a wide variety of samples. The sequence of those processes being optimised. A device, instrument using the device and method of use are also provided which offer reliable performance of a heating based process, with minimal condensation and/or sample loss issues. | 09-02-2010 |
20100267092 | COMPONENTS - A method and device structure are provided which enable an archive sample to be collected and detached relative to a device within which a series of processes, such as PCR are being provided. A chamber structure and method of use are provided in which a controlled and precise volume is obtained by control of the relative resistance to flow through various channels. | 10-21-2010 |
20110100101 | PERFORMANCE - Instruments, devices and methods of analysis are provided which fully integrate a significant number of process steps in a continuous operation. Accurate positioning and full contact between components is also provided by the relative movement the designs allow. An effect interface between a low cost disposable cartridge or device and the instrument to process it is also detailed. | 05-05-2011 |
20120034601 | Porous Materials for Biological Sample Collection - Methods, apparatuses, and systems for collecting samples using hybrid porous materials that include an organic material and an inorganic material. A method for sample collection includes contacting a hybrid porous material and a biological sample to the porous material. The hybrid porous material includes an inorganic material and an organic material. The method includes placing the porous material with the attached sample in a liquid medium, wherein the sample is separated from the porous material in the liquid medium to form a separated sample, and collecting the separated sample in the medium. | 02-09-2012 |
20130130365 | DEVICES - A method of analysis, instrument for analysis and device for use in such an instrument are provided, which perform a number of processes need to reach a useful result in the context of a wide variety of samples. The sequence of those processes being optimised. A device, instrument using the device and method of use are also provided which offer reliable performance of a heating based process, with minimal condensation and/or sample loss issues. | 05-23-2013 |
20130135618 | ANALYSIS - Analysis methods and apparatus are provided for inspecting a channel, such as a capillary electrophoresis channel, in a device. Configuration and alignment systems are provided, together with optical systems and temperature control. | 05-30-2013 |
20130323737 | METHOD AND SYSTEM FOR ANALYZING A SAMPLE - A method and system for analysing a sample are provided, wherein one or more process steps and/or sample processors are provided separately from the instrument, for instance a sample receiving step and sample preparation step and sample extraction step and sample retention step and/or purification step and washing step and elution step, and one or more process steps and/or sample processors provided by the instrument as an integrated set, the one or more process steps and/or sample processors provided by the instrument including a sample receiving step and amplification step and denaturing step and investigation step and detection step and results analysis step and results output step. Other combinations of the split in location of the steps are possible. The optimisation of the split allows the accurate processing by a cartridge based instrument of the sample, whilst fully interfacing with a variety of sample collection and/or preparation approaches. | 12-05-2013 |
20140178938 | COMPONENTS - A method and device structure are provided which enable an archive sample to be collected and detached relative to a device within which a series of processes, such as PCR are being provided. A chamber structure and method of use are provided in which a controlled and precise volume is obtained by control of the relative resistance to flow through various channels. | 06-26-2014 |
20140186841 | SENSING AND IDENTIFYING BIOLOGICAL SAMPLES ON MICROFLUIDIC DEVICES - A method, system, and apparatus for analysis of a biological sample includes receiving the sample, wherein the sample includes deoxyribonucleic acid (DNA), lysing the sample to obtain access to the DNA included in the sample, purifying the DNA in the sample to isolate the DNA from other components in the sample, amplifying the DNA, separating fragments of the amplified DNA, detecting the separated fragments using laser induced fluorescence, based on the detecting, generating a profile of the DNA in the received sample, comparing the generated profile with profiles of DNA stored in a database, and upon determining that the generated profile matches one of the stored profiles, identifying the source from which the stored profile was obtained, wherein the receiving, lysing, purifying, amplifying, and detecting are performed on corresponding portions of a microfluidic device, and wherein transporting the sample and the DNA to the portions of the microfluidic device and enabling the lysing, purifying, amplifying, separating, detecting, generating, comparing, and identifying are performed automatically without user interaction. | 07-03-2014 |
20150238958 | MICROFLUIDIC DEVICE FOR BIOLOGICAL SAMPLE PREPARATION - The present invention provides a microfluidic device for preparing or extracting a biological sample from a solid material and methods for using the same. The microfluidic device of the invention automates the biological sample extraction from a solid material, thereby significantly reducing the possibility of contamination, human error and a potential variability of the sample that is obtained by different technicians. | 08-27-2015 |
Patent application number | Description | Published |
20130272368 | LOW POWER DATA RECOVERY USING OVER-CLOCKING - Described herein are apparatus, system, and method for low power data recovery using over-clocking. The apparatus is a receiver that comprises an edge detector to detect a first falling edge and a first rising edge of an input signal received from a transmitter; a counter to count in a first direction in response to detecting the first falling edge, and to count in a second direction in response to detecting the first rising edge of the input signal, the counter to generate a final count value based on the counts in the first and second directions; and a decision unit to determine whether data in the input signal is of logical high or logical low value, the determination made according to the final count value, wherein the receiver and the transmitter are a Mobile Industry Processor Interface (MIPIĀ®) M-PHY | 10-17-2013 |
20130342248 | Low Power Oversampling With Delay Locked Loop Implementation - In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver. | 12-26-2013 |
20130342249 | Low Power Oversampling With Reduced-Architecture Delay Locked Loop - In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver. | 12-26-2013 |
20140002153 | LOW POWER DATA RECOVERY | 01-02-2014 |
20140002283 | DATA INTERFACE ALIGNMENT | 01-02-2014 |
20140006840 | DATA INTERFACE SLEEP MODE LOGIC | 01-02-2014 |
20140015581 | DATA INTERFACE CLOCK GENERATION - In one embodiment, an apparatus may include a clock generator to generate a format clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the format clock signal and the serial data. | 01-16-2014 |
20140086363 | PULSE WIDTH MODULATION RECEIVER CIRCUITRY - Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data signal, where a count is started in response to the bit being subsequently shifted out of the shift circuit. Based on a value of the count, the receiver circuit generates a control signal for preparing physical layer receiver logic to transition to a burst mode of operation. In another embodiment, a receiver circuit includes a frequency divider to operate based on a data signal and a clock signal, wherein, based on operation of the frequency counter, a control signal is generated to indicate a line reset for physical layer receiver logic. The receiver circuit provides a feedback signal, based on the control signal, which is to limit activation of the frequency divider. | 03-27-2014 |
20140103978 | LOW POWER DATA RECOVERY - In one embodiment, an apparatus may include a pulse generator to generate an oversampled clock signal. The apparatus may also include a sample and hold unit to provide at least two differential input signals based on the oversampled clock signal. The apparatus may further include a conversion unit to generate a single-ended signal based on the at least two differential input signals. The apparatus may also include a counter to determine a count of rising and falling edges of the single-ended signal based on the oversampled clock signal. | 04-17-2014 |
20140159780 | DATA INTERFACE CLOCK GENERATION - In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data. | 06-12-2014 |
20140211894 | DATA INTERFACE SYNCHRONIZATION - In one embodiment, an apparatus may include a de-serializer to convert serial data to parallel data, and a counter to provide an update signal based on a bit count of the serial data. The apparatus may further include a synchronizer to provide a synchronization signal when a target clock signal is synchronized with the update signal. The apparatus may further include an output unit to provide a validation indicator in response to the synchronization signal. | 07-31-2014 |
20140294060 | Low Power Oversampling With Delay Locked Loop Implementation - In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver. | 10-02-2014 |
20140369400 | Low Power Oversampling With Reduced-Architecture Delay Locked Loop - In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver. | 12-18-2014 |