Patent application number | Description | Published |
20080234246 | ANALOGS OF ANSAMYCIN AND PHARMACEUTICAL COMPOSITIONS THEREOF - Analogs of geldanamycin (an ansamycin), pharmaceutical formulations comprising such analogs, and methods of use (e.g., treating tumors). | 09-25-2008 |
20080275100 | PROPOFOL ANALOGS, PROCESS FOR THEIR PREPARATION, AND METHODS OF USE - The invention provides para substituted dialkylphenol derivatives of propofol. The invention further provides pharmaceutical compositions comprising such analogs, methods for preparing such analogs, and methods of using such analogs to induce general anesthesia, sedation, and/or hypnotic or sleep effects in a patient. | 11-06-2008 |
20090130163 | Drugs With Improved Hydrophobicity For Incorporation in Medical Devices - The invention provides a medical device comprising a hydrophobic analog of a medicament known to inhibit cell proliferation and migration. The invention also provides a method of treating a narrowing in a body passageway comprising placing an implantable medical device comprising a hydrophobic analog of a medicament known to inhibit cell proliferation and migration. The medicaments can be incorporated within or coated on the device. The invention further provides hydrophobic analogs of medicaments known to inhibit cell proliferation and migration. | 05-21-2009 |
20090263483 | NANOPARTICLE FORMULATIONS AND USES THEREOF - The present invention provides compositions comprising nanoparticles comprising: 1) a drug, such as a hydrophobic drug derivative; and 2) a carrier protein. Also provided are methods of treating diseases (such as cancer) using the compositions, as well as kits and unit dosages. | 10-22-2009 |
20100160448 | COMPOSITIONS, METHODS OF USE AND PREPARATION OF 2,6-DIISOPROPYL PHENOL AND ANALOGS FOR ISCHEMIC INJURY - The present invention provides novel 2,6-diisopropyl phenol 2,6-diisopropyl phenol analogs and sterile, stable pharmaceutical compositions of 2,6-diisopropyl phenol 2,6-diisopropyl phenol and analogs thereof useful as an antioxidant in the treatment of ischemic injury including stroke and other cerebral injury. 2,6-diisopropyl phenol or its analogs are administered in a dosage effective to produce blood levels and brain levels of the drug that can prevent free radical damage associated with ischemic injury. | 06-24-2010 |
20100279963 | DICARBONYL DERIVATIVES AND METHODS OF USE - Derivatives of dicarbonyl compounds having antitumor and antibiotic activity which can be used as anticancer agents. | 11-04-2010 |
20100305148 | DI-ESTER PRODRUGS OF CAMPTOTHECIN, PROCESS FOR THEIR PREPARATION AND THEIR THERAPEUTICAL APPLICATIONS - The present invention is related to 10,20-di-O ester derivatives of camptothecin and pharmaceutical formulations thereof. The compounds and pharmaceutical formulations of the present invention possess increased biological life span and bioavailability and reduced toxicity, while maintaining anti-cancer activity. | 12-02-2010 |
20110150763 | TRIAZINE DERIVATIVES AND THEIR THERAPEUTICAL APPLICATIONS - The invention provides for Triazine derivatives and their use to modulate protein kinase activity in a variety of conditions and diseases. | 06-23-2011 |
20120172361 | TRIAZINE DERIVATIVES AND THEIR THERAPEUTICAL APPLICATIONS - Compounds of the formula (I) and formula (II) and pharmaceutically acceptable salts thereof. | 07-05-2012 |
20120178758 | STYRYL-TRIAZINE DERIVATIVES AND THEIR THERAPEUTICAL APPLICATIONS - The invention provides Styryl-Triazine derivatives, and further provides methods of using these compounds to modulate protein kinases and to treat protein kinase mediated diseases. | 07-12-2012 |
20120196860 | Triazine derivatives and their therapeutical applications - The invention provides Triazine derivatives and further provides methods of using these compounds to modulate protein kinases and for treating diseases and conditions mediated by protein kinases. | 08-02-2012 |
20120202818 | UREIDOPHENYL SUBSTITUTED TRIAZINE DERIVATIVES AND THEIR THERAPEUTICAL APPLICATIONS - The present invention provides Uredophenyl substituted triazine derivatives and provides methods of using these compounds to modulate protein kinases and methods of using these compounds to treat protein kinase mediated diseases and conditions. | 08-09-2012 |
20120231082 | NOVEL FORMULATIONS OF PHARMACOLOGICAL AGENTS, METHODS FOR THE PREPARATION THEREOF AND METHODS FOR THE USE THEREOF - In accordance with the present invention, there are provided compositions and methods useful for the in vivo delivery of substantially water insoluble pharmacologically active agents (such as the anticancer drug paclitaxel) in which the pharmacologically active agent is delivered in the form of suspended particles coated with protein (which acts as a stabilizing agent). In particular, protein and pharmacologically active agent in a biocompatible dispersing medium are subjected to high shear, in the absence of any conventional surfactants, and also in the absence of any polymeric core material for the particles. The procedure yields particles with a diameter of less than about 1 micron. The use of specific composition and preparation conditions (e.g., addition of a polar solvent to the organic phase), and careful selection of the proper organic phase and phase fraction, enables the reproducible production of unusually small nanoparticles of less than 200 nm diameter, which can be sterile-filtered. The particulate system produced according to the invention can be converted into a redispersible dry powder comprising nanoparticles of water-insoluble drug coated with a protein, and free protein to which molecules of the pharmacological agent are bound. This results in a unique delivery system, in which part of the pharmacologically active agent is readily bioavailable (in the form of molecules bound to the protein), and part of the agent is present within particles without any polymeric matrix therein. | 09-13-2012 |
20120238576 | Triazine Derivatives and their Therapeutical Applications - The present invention comprises inter alia compounds as shown in formula (I) or a pharmaceutically acceptable salt thereof. | 09-20-2012 |
20120264759 | BENZYL SUBSTITUTED TRIAZINE DERIVATIVES AND THEIR THERAPEUTICAL APPLICATIONS - The invention provides triazine compounds and methods of their use to modulate protein kinases and to treat diseases mediated by said protein kinases. | 10-18-2012 |
20120270858 | Isoquinoline, quinoline, and quinazoline derivatives as inhibitors of hedgehog signaling - The invention provides isoquinoline, quinoline, and quinazoline derivatives to treat a variety of disorders, diseases and pathologic conditions, and more specifically to the use of isoquinoline, quinoline, and quinazoline derivatives to inhibit the hedgehog signaling pathway and to the use of those compounds to the treatment of hyperproliferative diseases and pathologic angiogenesis. | 10-25-2012 |
20120277233 | Pyridyl-Triazine Inhibitors of Hedgehog Signaling - The invention provides pyridyl-triazine derivatives to inhibit the hedgehog signaling pathway and the use of such compounds in the treatment of hyperproliferative diseases and angiogenisis mediated diseases. | 11-01-2012 |
20130023497 | Triazine Derivatives and their Therapeutical Applications - The present invention comprises inter alia triazine compounds as shown in formula (I) and pharmaceutically acceptable salts thereof. | 01-24-2013 |
20130045240 | COMBINATION THERAPY WITH NANOPARTICLE COMPOSITIONS OF TAXANE AND HEDGEHOG INHIBITORS - The present invention provides combination therapy methods of treating a proliferative disease (such as cancer) comprising administering to an individual an effective amount of a taxane in a nanoparticle composition, and a hedgehog inhibitor that inhibits a hedgehog signaling pathway. | 02-21-2013 |
20130195983 | NANOPARTICLE FORMULATIONS AND USES THEREOF - The present invention provides compositions comprising nanoparticles comprising: 1) a drug, such as a hydrophobic drug derivative; and 2) a carrier protein. Also provided are methods of treating diseases (such as cancer) using the compositions, as well as kits and unit dosages. | 08-01-2013 |
20140072630 | COMBINATION THERAPY WITH NANOPARTICLE COMPOSITIONS OF TAXANE AND HEDGEHOG INHIBITORS - The present invention provides combination therapy methods of treating a proliferative disease (such as cancer) comprising administering to an individual an effective amount of a taxane in a nanoparticle composition, and a hedgehog inhibitor that inhibits a hedgehog signaling pathway. | 03-13-2014 |
20140080901 | NANOPARTICLE FORMULATIONS AND USES THEREOF - The present invention provides compositions comprising nanoparticles comprising: 1) a drug, such as a hydrophobic drug derivative; and 2) a carrier protein. Also provided are methods of treating diseases (such as cancer) using the compositions, as well as kits and unit dosages. | 03-20-2014 |
20140302157 | NANOPARTICLE FORMULATIONS AND USES THEROF - The present invention provides compositions comprising nanoparticles comprising: 1) a drug, such as a hydrophobic drug derivative; and 2) a carrier protein. Also provided are methods of treating diseases (such as cancer) using the compositions, as well as kits and unit dosages. | 10-09-2014 |
20150111960 | NOVEL FORMULATIONS OF PHARMACOLOGICAL AGENTS, METHODS FOR THE PREPARATION THEREOF AND METHODS FOR THE USE THEREOF - In accordance with the present invention, there are provided compositions and methods useful for the in vivo delivery of substantially water insoluble pharmacologically active agents (such as the anticancer drug paclitaxel) in which the pharmacologically active agent is delivered in the form of suspended particles coated with protein (which acts as a stabilizing agent). In particular, protein and pharmacologically active agent in a biocompatible dispersing medium are subjected to high shear, in the absence of any conventional surfactants, and also in the absence of any polymeric core material for the particles. The procedure yields particles with a diameter of less than about 1 micron. The use of specific composition and preparation conditions (e.g., addition of a polar solvent to the organic phase), and careful selection of the proper organic phase and phase fraction, enables the reproducible production of unusually small nanoparticles of less than 200 nm diameter, which can be sterile-filtered. The particulate system produced according to the invention can be converted into a redispersible dry powder comprising nanoparticles of water-insoluble drug coated with a protein, and free protein to which molecules of the pharmacological agent are bound. This results in a unique delivery system, in which part of the pharmacologically active agent is readily bioavailable (in the form of molecules bound to the protein), and part of the agent is present within particles without any polymeric matrix therein. | 04-23-2015 |
Patent application number | Description | Published |
20090283721 | NITRIDE-BASED RED PHOSPHORS - Embodiments of the present invention are directed to the fluorescence of a nitride-based deep red phosphor having at least one of the following novel features: 1) an oxygen content less than about 2 percent by weight, and 2) a halogen content. Such phosphors are particularly useful in the white light illumination industry, which utilizes the so-called “white LED.” The selection and use of a rare earth halide as a raw material source of not only the activator for the phosphor, but also the halogen, is a key feature of the present embodiments. The present phosphors have the general formula M | 11-19-2009 |
20090294731 | SILICATE-BASED GREEN PHOSPHORS - Novel green phosphors are disclosed having the comprise silicate-based compounds having the formula (Sr,A | 12-03-2009 |
20100019202 | Two-Phase Silicate-Based Yellow Phosphor - Novel two-phase yellow phosphors are disclosed having a peak emission intensity at wavelengths ranging from about 555 nm to about 580 nm when excited by a radiation source having a wavelength ranging from 220 nm to 530 nm. The present phosphors may be represented by the formula a[Sr | 01-28-2010 |
20100308712 | NITRIDE-BASED RED-EMITTING PHOSPHORS IN RGB RED-GREEN-BLUE LIGHTING SYSTEMS - Embodiments of the present invention are directed to nitride-based, red-emitting phosphors in red, green, and blue (RGB) lighting systems, which in turn may be used in backlighting displays and warm white-light applications. In particular embodiments, the red-emitting phosphor is based on CaAlSiN | 12-09-2010 |
20120175557 | NANO-YAG:CE PHOSPHOR COMPOSITIONS AND THEIR METHODS OF PREPARATION - Disclosed herein are cerium doped, garnet phosphors emitting in the yellow region of the spectrum, and having the general formula (Y,A) | 07-12-2012 |
20130127332 | Coatings for Photoluminescent Materials - The teachings are generally directed to phosphors having combination coatings with multifunctional characteristics that increase the performance and/or reliability of the phosphor. The teachings include highly reliable phosphors having coatings that contain more than one inorganic component, more than one layer, more than one thicknesses, more than one combination of layers or thicknesses, a gradient-interface between components, a primer thickness or layer to inhibit or prevent leaching of phosphor components into the coatings, a sealant layer to inhibit or prevent entry of moisture or oxygen from the environment, a mixed composition layer as a sealant and multifunctional combination coatings. | 05-23-2013 |
20130168605 | NITRIDE PHOSPHORS WITH INTERSTITIAL CATIONS FOR CHARGE BALANCE - Phosphors comprising a nitride-based composition represented by the chemical formula: M | 07-04-2013 |
20130234586 | Nitride-Based Red-Emitting Phosphors in RGB (Red-Green-Blue) Lighting Systems - Embodiments of the present invention are directed to nitride-based, red-emitting phosphors in red, green, and blue (RGB) lighting systems, which in turn may be used in backlighting displays and warm white-light applications. In particular embodiments, the red-emitting phosphor is based on CaAlSiN | 09-12-2013 |
20130234589 | Red-Emitting Nitride-Based Phosphors - A red-emitting phosphor comprises a nitride-based composition represented by the chemical formula M | 09-12-2013 |
20140042365 | GREEN-EMITTING (OXY)NITRIDE-BASED PHOSPHORS AND LIGHT-EMITTING DEVICE USING THE SAME - A green-emitting phosphor having the formula A | 02-13-2014 |
20140055982 | White Light Illumination System with Narrow Band Green Phosphor and Multiple-Wavelength Excitation - A white light illumination system may comprise: a phosphor package; a first radiation source for providing co-excitation radiation to the phosphor package, the source emitting in wavelengths ranging from about 250 nm to about 410 nm; and a second radiation source for providing co-excitation radiation to the phosphor package, the source emitting in wavelengths ranging from about 410 nm to about 540 nm; wherein the phosphor package is configured to emit photoluminescence in wavelengths ranging from about 440 nm to about 700 nm upon co-excitation from the first and second radiation sources, and wherein the phosphor package comprises at least one narrow band green phosphor with a photoluminescence peak with a full width at half maximum of less than 60 nm, and wherein the narrow band green phosphor is configured to emit photoluminescence in wavelengths ranging from about 500 nm to about 550 nm. | 02-27-2014 |
20140084783 | RED-EMITTING NITRIDE-BASED CALCIUM-STABLIZED PHOSPHORS - Red-emitting phosphors may comprise a nitride-based composition represented by the chemical formula M | 03-27-2014 |
20140158935 | Green-Emitting, Garnet-Based Phosphors in General and Backlighting Applications - Disclosed herein are green-emitting, garnet-based phosphors having the formula (Lu | 06-12-2014 |
20140361681 | RED-EMITTING NITRIDE-BASED PHOSPHORS - A red-emitting phosphor comprises a nitride-based composition represented by the chemical formula M | 12-11-2014 |
20150022998 | White Light Illumination System with Narrow Band Green Phosphor and Multiple-Wavelength Excitation - A white light illumination system may comprise: a phosphor package; a first radiation source for providing co-excitation radiation to the phosphor package, the source emitting in wavelengths ranging from about 250 nm to about 410 nm; and a second radiation source for providing co-excitation radiation to the phosphor package, the source emitting in wavelengths ranging from about 410 nm to about 540 nm; wherein the phosphor package is configured to emit photoluminescence in wavelengths ranging from about 440 nm to about 700 nm upon co-excitation from the first and second radiation sources, and wherein the phosphor package comprises at least one narrow band green phosphor with a photoluminescence peak with a full width at half maximum of less than 60 nm, and wherein the narrow band green phosphor is configured to emit photoluminescence in wavelengths ranging from about 500 nm to about 550 nm. | 01-22-2015 |
20150284628 | Coatings for Photoluminescent Materials - The teachings are generally directed to phosphors having combination coatings with multifunctional characteristics that increase the performance and/or reliability of the phosphor. The teachings include highly reliable phosphors having coatings that contain more than one inorganic component, more than one layer, more than one thicknesses, more than one combination of layers or thicknesses, a gradient-interface between components, a primer thickness or layer to inhibit or prevent leaching of phosphor components into the coatings, a sealant layer to inhibit or prevent entry of moisture or oxygen from the environment, a mixed composition layer as a sealant and multifunctional combination coatings. | 10-08-2015 |
20150284629 | Nitride Phosphors with Interstitial Cations for Charge Balance - Phosphors comprising a nitride-based composition represented by the chemical formula: M | 10-08-2015 |
20150315464 | Nitride-Based Red-Emitting Phosphors in RGB (Red-Green-Blue) Lighting Systems - Embodiments of the present invention are directed to nitride-based, red-emitting phosphors in red, green, and blue (RGB) lighting systems, which in turn may be used in backlighting displays and warm white-light applications. In particular embodiments, the red-emitting phosphor is based on CaAlSiN | 11-05-2015 |
20150376497 | GREEN-EMITTING, GARNET-BASED PHOSPHORS IN GENERAL AND BACKLIGHTING APPLICATIONS - Disclosed herein are green-emitting, garnet-based phosphors having the formula (Lu | 12-31-2015 |
Patent application number | Description | Published |
20090285010 | Write Assist Circuit for Improving Write Margins of SRAM Cells - A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines. | 11-19-2009 |
20100246311 | CLOCK GENERATORS, MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING AN INTERNAL CLOCK SIGNAL - A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period. | 09-30-2010 |
20110280096 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS - A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers. | 11-17-2011 |
20120014201 | DUAL RAIL MEMORY - A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column. | 01-19-2012 |
20120019312 | RECYCLING CHARGES - A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised. | 01-26-2012 |
20120020169 | TWO-PORT SRAM WRITE TRACKING SCHEME - A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation. | 01-26-2012 |
20120020176 | GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS - Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain. | 01-26-2012 |
20120061764 | MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE - The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas. | 03-15-2012 |
20120182819 | RECYCLING CHARGES - A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised. | 07-19-2012 |
20120206983 | TRACKING SCHEME FOR MEMORY - A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row. | 08-16-2012 |
20120230127 | Providing Row Redundancy to Solve Vertical Twin Bit Failures - A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory. | 09-13-2012 |
20130010560 | GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS - A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node. | 01-10-2013 |
20130088925 | LAYOUT OF MEMORY CELLS - A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region. | 04-11-2013 |
20130088926 | TRACKING MECHANISMS - A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro. | 04-11-2013 |
20130088927 | SYSTEM AND METHOD FOR GENERATING A CLOCK - A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking transition of a tracking signal is caused by the second clock. Based on a later transition of a second clock transition of the first clock and the tracking transition of the tracking signal, a second transition of the third clock is generated. The third clock is for use by an input-output of the memory macro. | 04-11-2013 |
20130182512 | MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS - A circuit including a memory circuit, the memory circuit includes a first plurality of memory arrays and a first plurality of keepers, each keeper of the first plurality of keepers is electrically coupled with a corresponding one of the first plurality of memory arrays. The memory circuit further includes a first current limiter electrically coupled with and shared by the first plurality of keepers. | 07-18-2013 |
20130215693 | TRACKING CAPACITIVE LOADS - A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell. | 08-22-2013 |
20130264718 | LAYOUT OF MEMORY STRAP CELL - A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source. | 10-10-2013 |
20130311964 | MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE - A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device. | 11-21-2013 |
20140015582 | SLICER AND METHOD OF OPERATING THE SAME - This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal. | 01-16-2014 |
20140032871 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell. | 01-30-2014 |
20140085993 | MULTIPLE BITCELLS TRACKING SCHEME SEMICONDUCTOR MEMORY ARRAY - A read tracking system and method for advanced memory devices are provided. The read tracking system and method include tracking multiple tracking bit cells in multiple segments and columns to incorporate device performance variation of bit cells in the memory array. The tracking path mimics the worst-case read path with some built-in margins to sufficiently and efficiently cover the read times of bit cells in a memory array without unnecessarily sacrificing the read speed performance of the memory array. A number of tracking cells may be placed at different segments and both sides of the memory array to cover read time variation across memory array. | 03-27-2014 |
20140092675 | TWO-PORT SRAM WRITE TRACKING SCHEME - A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells. The write tracking control circuit further includes a first delay circuit between the input node and the first transistor, the first delay circuit configured to introduce a first delay time, wherein a gate of the first transistor is connected to the first delay circuit. The write tracking control circuit further includes a second delay circuit between the input node and the second transistor, the second delay circuit configured to introduce a second delay time different from the first delay time, wherein a gate of the second transistor is connected to the second delay circuit. | 04-03-2014 |
20140119426 | SLICER AND METHOD OF OPERATING THE SAME - A slicer includes a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal. The first latch further includes a developing transistor configured to receive a second clock signal, wherein the first clock signal is different from the second clock signal. The first latch further includes a first input transistor configured to receive a first input. The first latch further includes a second input transistor configured to receive a second input, wherein the first and second input transistors are connected with the developing transistor. The first latch further includes at least one pre-charging transistor configured to receive a third clock signal, wherein the at least one pre-charging transistor is connected to a first output node and a second output node. The slicer further includes a second latch connected to the first and second output nodes and to a third output node. | 05-01-2014 |
20140138776 | CELL CIRCUITS AND LAYOUTS USED IN WRITE TRACKING CIRCUITS AND READ TRACKING CIRCUITS - A circuit includes a first transistor and a second transistor of a first type, a first transistor, a second transistor, a third transistor, and a fourth transistor of a second type. The first and second transistors of the first type, and the first transistor and the second transistor of the second type form a cross latch having a first node and a second node. A first terminal of the third transistor of the second type is coupled with the first node. A first terminal of the fourth transistor of the second type is coupled with the second node. At least one of a second terminal of the third transistor of the second type or a second terminal of the fourth transistor of the second type is configured to receive a signal sufficient to turn off the third transistor or the fourth transistor that is not directly from a power source. | 05-22-2014 |
20140140158 | PRE-CHARGING A DATA LINE - A control circuit includes a data driver, a charge circuit, and a first data line coupled with the data driver and the charge circuit. The charge circuit is configured to charge the first data line when the first data line is selected for accessing a memory cell corresponding to the first data line and to not charge the first data line when the first data line is not selected for accessing the memory cell. The data driver, based on a first control signal, is configured to transfer a signal on the first data line to an output of the data driver. | 05-22-2014 |
20140247675 | MULTIPLE BITCELLS TRACKING SCHEME SEMICONDUCTOR MEMORY ARRAY - A memory array includes a memory segment having at least one memory bank. The at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank. The memory array further includes a read tracking circuit coupled to the at least two first read tracking cells. Outputs of the at least two first read tracking cells are connected to a tracking bit connection line (TBCL). A tracking circuit connected to the TBCL is configured to output a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry. The memory control circuitry is configured to reset a memory clock based on the global tracking result signal. | 09-04-2014 |
20140269026 | TRACKING CIRCUIT - A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal. | 09-18-2014 |
20140282318 | TIMING DELAY CHARACTERIZATION METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay. | 09-18-2014 |
20140282319 | SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted. | 09-18-2014 |
20150029797 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line. | 01-29-2015 |
20150071016 | TRACKING MECHANISMS - A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated. | 03-12-2015 |
20150095867 | SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block. | 04-02-2015 |
20150131391 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal. | 05-14-2015 |
20150162060 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line. | 06-11-2015 |
20150178430 | TIMING DELAY CHARACTERIZATION METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay. The processor is further configured to generate timing delays of the memory circuit based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay. | 06-25-2015 |
20150213858 | READING DATA FROM A MEMORY CELL - In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction. | 07-30-2015 |
20150294715 | PRE-CHARGING A DATA LINE - A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory cells associated with the signal generating circuit. A first state of the pre-charge signal depends on a first state of the column select signal, and the first state of the column select signal corresponds to selection of the column of memory cells. The circuit also includes a charge circuit associated with the signal generating circuit and a first data line coupled to the charge circuit. The charge circuit charges the first data line in response to the first state of the pre-charge signal and allows the first data line to float in response to a second state of the pre-charge signal. | 10-15-2015 |
20150325287 | MEMORY ARRAY AND METHOD OF OPERATING THE SAME - A memory array includes an array of memory cells. The memory array further includes at least two read tracking cells in a read tracking column. The memory array further includes a read tracking circuit coupled to the at least two read tracking cells, wherein the read tracking circuit is configured to generate a global tracking result signal based on outputs from the at least two read tracking cells. The memory array further includes memory control circuitry, wherein the memory control circuitry is configured to reset a memory clock based on the global tracking result signal. | 11-12-2015 |
Patent application number | Description | Published |
20080200349 | MICRODEVICES HAVING A PREFERENTIAL AXIS OF MAGNETIZATION AND USES THEREOF - This invention relates generally to the field of moiety or molecule isolation, detection and manipulation and library synthesis. In particular, the invention provides a microdevice, which microdevice comprises: a) a magnetizable substance; and b) a photorecognizable coding pattern, wherein said microdevice has a preferential axis of magnetization. Systems and methods for isolating, detecting and manipulating moieties and synthesizing libraries using the microdevices are also provided. | 08-21-2008 |
20080206757 | METHODS AND COMPOSITIONS FOR DETECTING RARE CELLS FROM A BIOLOGICAL SAMPLE - The present invention provides methods and compositions for isolating and detecting rare cells from a biological sample containing other types of cells. In particular, the present invention includes a debulking step that uses a microfabricated filters for filtering fluid samples and the enriched rare cells can be used in a downstream process such as identifies, characterizes or even grown in culture or used in other ways. The invention also include a method of determining the aggressiveness of the tumor or of the number or proportion of cancer cells in the enriched sample by detecting the presence or amount of telomerase activity or telomerase nucleic acid or telomerase expression after enrichment of rare cells. This invention further provides an efficient and rapid method to specifically remove red blood cells as well as white blood cells from a biological sample containing at least one of each of red blood cells and white blood cells, resulting in the enrichment of rare target cells including circulating tumor cells (CTC), stromal cells, mesenchymal cells, endothelial cells, fetal cells, stem cells, non-hematopoietic cells etc from a blood sample. The method is based upon combination of immuno-microparticles (antibody coated microparticles) and density-based separation. The final enriched target cells can be subjected to a variety of analysis and manipulations, such as flowcytometry, PCR, immunofluorescence, immunocytochemistry, image analysis, enzymatic assays, gene expression profiling analysis, efficacy tests of therapeutics, culturing of enriched rare cells, and therapeutic use of enriched rare cells. In addition, depleted plasma protein and white blood cells can be optionally recovered, and subjected to other analysis such as inflammation studies, gene expression profiling, etc. | 08-28-2008 |
20100260984 | MICRODEVICES CONTAINING PHOTORECOGNIZABLE CODING PATTERNS AND METHODS OF USING AND PRODUCING THE SAME - This invention relates generally to the field of moiety or molecule analysis, isolation, detection and manipulation and library synthesis. In particular, the invention provides a microdevice, which microdevice comprises: a) a substrate; and b) a photorecognizable coding pattern on said substrate. Preferably, the microdevice does not comprise an anodized metal surface layer. Methods and kits for isolating, detecting and manipulating moieties, and synthesizing libraries using the microdevices are also provided. The invention further provides two-dimensional optical encoders and uses thereof. In certain embodiments, the invention provides a microdevice, which microdevice comprises: a) a magnetizable substance; and b) a photorecognizable coding pattern, wherein said microdevice has a preferential axis of magnetization. Systems and methods for isolating, detecting and manipulating moieties and synthesizing libraries using the microdevices are also provided. | 10-14-2010 |
20120228386 | MICRODEVICES CONTAINING PHOTORECOGNIZABLE CODING PATTERNS AND METHODS OF USING AND PRODUCING THE SAME - This invention relates generally to the field of moiety or molecule analysis, isolation, detection and manipulation and library synthesis. In particular, the invention provides a microdevice, which microdevice comprises: a) a substrate; and b) a photorecognizable coding pattern on said substrate. Preferably, the microdevice does not comprise an anodized metal surface layer. Methods and kits for isolating, detecting and manipulating moieties, and synthesizing libraries using the microdevices are also provided. The invention further provides two-dimensional optical encoders and uses thereof. In certain embodiments, the invention provides a microdevice, which microdevice comprises: a) a magnetizable substance; and b) a photorecognizable coding pattern, wherein said microdevice has a preferential axis of magnetization. Systems and methods for isolating, detecting and manipulating moieties and synthesizing libraries using the microdevices are also provided. | 09-13-2012 |
20140073536 | METHODS AND COMPOSITIONS FOR DETECTING NON-HEMATOPOIETIC CELLS FROM A BLOOD SAMPLE - The present invention recognizes that diagnosis and prognosis of many conditions can depend on the enrichment of rare cells, especially tumor cells, from a complex fluid sample such as a blood sample. In particular, the present invention is directed to methods and compositions for detecting a non-hematopoietic cell, e.g., a non-hematopoietic tumor cell, in a blood sample via, inter alia, removing red blood cells (RBCs) from a blood sample using a non-centrifugation procedure, removing white blood cells (WBCs) from said blood sample to enrich a non-hematopoietic cell, if any, from said blood sample; and assessing the presence, absence and/or amount of said enriched non-hematopoietic cell. | 03-13-2014 |
20140087358 | METHODS AND COMPOSITIONS FOR DETECTING RARE CELLS FROM A BIOLOGICAL SAMPLE - The present invention provides methods and compositions for isolating and detecting rare cells from a biological sample containing other types of cells. In particular, the present invention includes a debulking step that uses a microfabricated filters for filtering fluid samples and the enriched rare cells can be used in a downstream process such as identifies, characterizes or even grown in culture or used in other ways. The invention also include a method of determining the aggressiveness of the tumor or of the number or proportion of cancer cells in the enriched sample by detecting the presence or amount of telomerase activity or telomerase nucleic acid or telomerase expression after enrichment of rare cells. This invention further provides an efficient and rapid method to specifically remove red blood cells as well as white blood cells from a biological sample. | 03-27-2014 |
20150079677 | METHODS AND COMPOSITIONS FOR SEPARATING RARE CELLS FROM FLUID SAMPLES - The present invention includes methods of enriching rare cells, such as cancer cells, from biological samples, such as blood samples. The methods include performing at least one debulking step on a blood sample and selectively removing at least one type undesirable component from the blood sample to obtain a blood sample that is enriched in a rare cell of interest. In some embodiments magnetic beads coupled to specific binding members are used to selectively removed components. | 03-19-2015 |
20150185184 | METHODS AND COMPOSITIONS FOR SEPARATING OR ENRICHING BLOOD CELLS - The present invention provides a filtration chamber comprising a microfabricated filter enclosed in a housing, wherein the surface of said filter and/or the inner surface of said housing are modified by vapor deposition, sublimation, vapor-phase surface reaction, or particle sputtering to produce a uniform coating; and a method for separating cells of a fluid sample, comprising: a) dispensing a fluid sample into the filtration chamber disclosed herein; and b) providing fluid flow of the fluid sample through the filtration chamber, wherein components of the fluid sample flow through or are retained by the filter based on the size, shape, or deformability of the components. | 07-02-2015 |
Patent application number | Description | Published |
20110267018 | AC COUPLED HYSTERETIC PWM CONTROLLER - This document discusses, among other things, an apparatus and method for a hysteretic controller for an inductor based power converter. The hysteretic controller can include a coupling circuit configured to provide feedback information to a hysteretic comparator, the feedback information including a DC component of a feedback voltage and an AC component of the signal indicative of current flow through the inductor, wherein the feedback voltage is a scaled representation of load voltage. | 11-03-2011 |
20120092046 | LOW POWER POWER-ON-RESET (POR) CIRCUIT - In one general aspect, an apparatus can include a first voltage detect circuit configured to produce an output signal at a first power supply voltage, and configured to be in a non-monitoring state at a second power supply voltage greater than the first power supply voltage. The apparatus can include a second voltage detect circuit configured to change from a non-monitoring state to a monitoring state and configured to produce an output signal at a third power supply voltage between the first power supply voltage and the second power supply voltage. The apparatus can also include a combination circuit configured to produce a power-on-reset signal based on a logical combination of the output signal produced by the first voltage detect circuit and the output signal produced by the second voltage detect circuit. | 04-19-2012 |
20120092059 | LOW SUPPLY NOISE POWER STAGE ARRANGEMENT FOR A SWITCH REGULATOR - In a general aspect, an apparatus can include a first switch configured to be coupled to a power source and configured to switch in response to an edge of a control signal. The apparatus can include delay circuit can be configured to produce a delay signal that has an edge corresponding to the edge of the control signal, the edge of the delay signal being offset from the edge of the control signal. The apparatus can also include a second switch can be configured to be coupled to the power source in parallel with the first switch and configured to switch in response to the edge of the delay signal, the second switch having a size smaller than a size of the first switch. | 04-19-2012 |
20120134407 | ADAPTIVE EQUALIZATION WITH GROUP DELAY - Methods, apparatuses, and systems are presented for performing adaptive equalization involving receiving a signal originating from a channel associated with inter-symbol interference, filtering the signal using a filter having a plurality of adjustable tap weights to produce a filtered signal, and adaptively updating each of the plurality of adjustable tap weights to a new value to reduce effects of inter-symbol interference, wherein each of the plurality of adjustable tap weights is adaptively updated to take into account a constraint relating to a measure of error in the filtered signal and a constraint relating to group delay associated with the filter. Each of the plurality of adjustable tap weights may be adaptively updated to drive group delay associated with the filter toward a target group delay. | 05-31-2012 |
20130263665 | MEMS DEVICE FRONT-END CHARGE AMPLIFIER - This document discusses, among other things, apparatus and methods for a front-end charge amplifier. In certain examples, a front-end charge amplifier for a microelectromechanical system (MEMS) device can include a charge amplifier configured to couple to the MEMS device and to provide sense information of a proof mass of the MEMS device, a feedback circuit configured to receive the sense information and to provide feedback to an input of the charge amplifier, and wherein the charge amplifier includes a transfer function having a first pole at a first frequency, a second pole at a second frequency, and one zero at a third frequency. | 10-10-2013 |
20130268227 | MEMS DEVICE AUTOMATIC-GAIN CONTROL LOOP FOR MECHANICAL AMPLITUDE DRIVE - This document discusses, among other things, apparatus and methods for digital automatic gain control for driving a MEMS device, such as a proof mass. In an example, an apparatus can include a driver configured to oscillate a proof mass of a MEMS device, a charge-to-voltage (C2V) converter configured to provide oscillation information of the proof mass, an analog-to-digital converter (ADC) configured to provide a digital representation of the oscillation information, and a digital, automatic gain control circuit to provide oscillation amplitude error information using a comparison of the oscillation information to target amplitude information, and to provide a digital drive command signal using an amplified representation of the oscillation amplitude error information. | 10-10-2013 |
20130268228 | MEMS DEVICE QUADRATURE SHIFT CANCELLATION - This document discusses, among other things, apparatus and methods quadrature cancelation of sense information from a micro-electromechanical system (MEMS) device, such as a MEMS gyroscope. In certain examples, a quadrature correction apparatus can include a drive charge-to-voltage (C2V) converter configured to provide drive information of a proof mass of a MEMS gyroscope, a sense C2V converter configured to provide sense information of the proof mass, a phase-shift module configured to provide phase shift information of the drive information, a drive demodulator configured to receive the drive information and the phase shift information and to provide demodulated drive information, a sense demodulator configured to receive the sense information and the phase shift information and to provide demodulated sense information, and wherein the quadrature correction apparatus is configured to provide corrected sense information using the demodulated drive information and the demodulated sense information. | 10-10-2013 |
20130269413 | MEMS QUADRATURE CANCELLATION AND SIGNAL DEMODULATION - In certain examples, a quadrature cancellation apparatus can include a drive charge amplifier configured to couple to a proof mass of a MEMS device and to provide oscillation motion information, a first sense charge amplifier configured to couple to the proof mass and to provide first sense information of a first movement of the MEMS device, a first programmable amplifier configured to receive the oscillation motion information and provide amplified oscillation motion information, a first summer configured to cancel quadrature error of the first sense information using the first sense information and the amplified oscillation motion information to provide quadrature-corrected first sense information, a phase shifter configured to receive the oscillation motion information and to provide carrier information, and a first multiplier configured to provide demodulated first sense information using the quadrature-corrected first sense information and the carrier information. | 10-17-2013 |
20130271228 | MICRO-ELECTRO-MECHANICAL-SYSTEM (MEMS) DRIVER - In an example, a driver for a micro-electro-mechanical-system (MEMS) device can include a first input configured to receive a first command signal including an oscillatory command signal, a second input configured to receive a second command signal including a bias command signal, and an amplifier configured to receive a high voltage supply, to provide, to the MEMS device, a closed-loop output signal responsive to both the first command signal and the second command signal in a first state, and to provide an open loop output signal configured to substantially span a voltage range of the high voltage supply in a second state. | 10-17-2013 |
Patent application number | Description | Published |
20090107834 | CHALCOGENIDE TARGET AND METHOD - A sputtering target for a sputtering chamber comprises a sputtering plate composed of a chalcogenide material comprising an average yield strength of from about 40 MPa to about 120 MPa and a thermal conductivity of at least about 2.8 W/(m·K). In one version the sputtering plate is composed of a chalcogenide material with a stoichiometric ratio that varies by less than about 5% throughout the body of the sputtering plate. In another version, the sputtering plate is composed of a chalcogenide material having an average grain size of at least 20 microns, and an oxygen content of less than 600 weight ppm. The sputtering target is sputtered by applying a pulsed DC voltage to the sputtering target. | 04-30-2009 |
20090233438 | SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING - A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets. | 09-17-2009 |
20100130007 | BOTTOM UP PLATING BY ORGANIC SURFACE PASSIVATION AND DIFFERENTIAL PLATING RETARDATION - Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. One embodiment provides a method provides a method for processing a substrate comprising forming a seed layer over a substrate having trench or via structures formed therein, coating a portion of the seed layer with an organic passivation film, and immersing the trench or via structures in a plating solution to deposit a conductive material over the seed layer not covered by the organic passivation film. | 05-27-2010 |
20120070982 | METHODS FOR FORMING LAYERS ON A SUBSTRATE - Methods for forming layers on a substrate having one or more features formed therein are provided herein. In some embodiments, a method for forming layers on a substrate having one or more features formed therein may include depositing a seed layer within the one or more features; and etching the seed layer to remove at least a portion of the seed layer proximate an opening of the feature such that the seed layer comprises a first thickness disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature and a second thickness disposed on an upper portion of the sidewall proximate the opening of the feature and wherein the first thickness is greater than the second thickness. | 03-22-2012 |
20130341794 | ULTRA-THIN COPPER SEED LAYER FOR ELECTROPLATING INTO SMALL FEATURES - An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. The presence of non-copper pre-electroplating material on the side walls allows the feature whose side walls, but not bottom surface, are lined with such pre-electroplating material (such as cobalt) to fill the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free. | 12-26-2013 |
20140305802 | SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING - A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets. | 10-16-2014 |
20140374907 | ULTRA-THIN COPPER SEED LAYER FOR ELECTROPLATING INTO SMALL FEATURES - An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. Modification of an upper portion of a metal seed layer allows for filling of the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free. | 12-25-2014 |
20150136732 | METHOD AND APPARATUS FOR FILM DEPOSITION - A method and apparatus for depositing films on a substrate is described. The method includes depositing a film on a substrate with feature formed therein or thereon. The feature includes a first surface and a second surface that are at different levels. A least a portion of the deposited film is removed by exposing the substrate to an ion flux from a linear ion source. The ion flux has an ion angular spread of less than or equal to 90 degrees and greater than or equal to 15 degrees. In certain embodiments, the feature can be a nanoscale, high aspect ratio feature such as narrow, deep trench, a small diameter, deep hole, or a dual damascene structure. Such features are often found in integrated circuit devices. | 05-21-2015 |
Patent application number | Description | Published |
20100051831 | LIGHT SOURCE EMPLOYING LASER-PRODUCED PLASMA - A system and a method of generating radiation and/or particle emissions are disclosed. In at least some embodiments, the system includes at least one laser source that generates a first pulse and a second pulse in temporal succession, and a target, where the target (or at least a portion the target) becomes a plasma upon being exposed to the first pulse. The plasma expand after the exposure to the first pulse, the expanded plasma is then exposed to the second pulse, and at least one of a radiation emission and a particle emission occurs after the exposure to the second pulse. In at least some embodiments, the target is a solid piece of material, and/or a time period between the first and second pulses is less than 1 microsecond (e.g., 840 ns). | 03-04-2010 |
20110122387 | SYSTEM AND METHOD FOR LIGHT SOURCE EMPLOYING LASER-PRODUCED PLASMA - A system and method of generating radiation are disclosed. In at least some embodiments, the system is suitable for use as (or as part of) an extreme ultraviolet lithography (EUVL) light source. Also, in at least some embodiments, the system includes a laser source for generating a laser pulse, a target including a solid material, and a lens device that assists in directing the laser pulse toward the target. At least a portion of the target becomes a plasma that emits radiation upon being exposed to the laser pulse. The laser pulse has a pulse duration of at least 50 nanoseconds and, in at least some such embodiments, has a pulse duration of at least 100 nanoseconds. | 05-26-2011 |
20140264087 | TARGET FOR LASER PRODUCED PLASMA EXTREME ULTRAVIOLET LIGHT SOURCE - Techniques for generating EUV light include directing a first pulse of radiation toward a target material droplet to form a modified droplet, the first pulse of radiation having an energy sufficient to alter a shape of the target material droplet; directing a second pulse of radiation toward the modified droplet to form an absorption material, the second pulse of radiation having an energy sufficient to change a property of the modified droplet, the property being related to absorption of radiation; and directing an amplified light beam toward the absorption material, the amplified light beam having an energy sufficient to convert at least a portion of the absorption material into extreme ultraviolet (EUV) light. | 09-18-2014 |
20140264090 | TARGET FOR LASER PRODUCED PLASMA EXTREME ULTRAVIOLET LIGHT SOURCE - Techniques for generating EUV light include directing a first pulse of radiation toward a target material droplet to form a modified droplet, the first pulse of radiation having an energy sufficient to alter a shape of the target material droplet; directing a second pulse of radiation toward the modified droplet to form an absorption material, the second pulse of radiation having an energy sufficient to change a property of the modified droplet, the property being related to absorption of radiation; and directing an amplified light beam toward the absorption material, the amplified light beam having an energy sufficient to convert at least a portion of the absorption material into extreme ultraviolet (EUV) light. | 09-18-2014 |
20140264092 | EXTREME ULTRAVIOLET LIGHT SOURCE - Techniques are described that enhance power from an extreme ultraviolet light source with feedback from a target material that has been modified prior to entering a target location into a spatially-extended target distribution or expanded target. The feedback from the spatially-extended target distribution provides a nonresonant optical cavity because the geometry of the path over which feedback occurs, such as the round-trip length and direction, can change in time, or the shape of the spatially-extended target distribution may not provide a smooth enough reflectance. However, it may be possible that the feedback from the spatially-extended target distribution provides a resonant and coherent optical cavity if the geometric and physical constraints noted above are overcome. In any case, the feedback can be generated using spontaneously emitted light that is produced from a non-oscillator gain medium. | 09-18-2014 |
20140299791 | TARGET FOR EXTREME ULTRAVIOLET LIGHT SOURCE - Techniques for forming a target and for producing extreme ultraviolet light include releasing an initial target material toward a target location, the target material including a material that emits extreme ultraviolet (EUV) light when converted to plasma; directing a first amplified light beam toward the initial target material, the first amplified light beam having an energy sufficient to form a collection of pieces of target material from the initial target material, each of the pieces being smaller than the initial target material and being spatially distributed throughout a hemisphere shaped volume; and directing a second amplified light beam toward the collection of pieces to convert the pieces of target material to plasma that emits EUV light. | 10-09-2014 |
20150076374 | TARGET FOR EXTREME ULTRAVIOLET LIGHT SOURCE - Techniques for forming a target and for producing extreme ultraviolet light include releasing an initial target material toward a target location, the target material including a material that emits extreme ultraviolet (EUV) light when converted to plasma; directing a first amplified light beam toward the initial target material, the first amplified light beam having an energy sufficient to form a collection of pieces of target material from the initial target material, each of the pieces being smaller than the initial target material and being spatially distributed throughout a hemisphere shaped volume; and directing a second amplified light beam toward the collection of pieces to convert the pieces of target material to plasma that emits EUV light. | 03-19-2015 |
20150189728 | Extreme Ultraviolet Light Source - A first remaining plasma that at least partially coincides with a target region is formed; a target including target material in a first spatial distribution to the target region is provided, the target material including material that emits EUV light when converted to plasma; the first remaining plasma and the initial target interact, the interaction rearranging the target material from the first spatial distribution to a shaped target distribution to form a shaped target in the target region, the shaped target including the target material arranged in the shaped spatial distribution; an amplified light beam is directed toward the target region to convert at least some of the target material in the shaped target to a plasma that emits EUV light; and a second remaining plasma is formed in the target region. | 07-02-2015 |
20150189729 | TARGET FOR LASER PRODUCED PLASMA EXTREME ULTRAVIOLET LIGHT SOURCE - Techniques for generating EUV light include directing a first pulse of radiation toward a target material droplet to form a modified droplet, the first pulse of radiation having an energy sufficient to alter a shape of the target material droplet; directing a second pulse of radiation toward the modified droplet to form an absorption material, the second pulse of radiation having an energy sufficient to change a property of the modified droplet, the property being related to absorption of radiation; and directing an amplified light beam toward the absorption material, the amplified light beam having an energy sufficient to convert at least a portion of the absorption material into extreme ultraviolet (EUV) light. | 07-02-2015 |
20150250045 | ADAPTIVE LASER SYSTEM FOR AN EXTREME ULTRAVIOLET LIGHT SOURCE - A system for an extreme ultraviolet (EUV) light source includes an optical amplifier including a gain medium positioned on a beam path, the optical amplifier configured to receive a light beam at an input and to emit an output light beam for an EUV light source at an output; a feedback system that measures a property of the output light beam and produces a feedback signal based on the measured property; and an adaptive optic positioned in the beam path and configured to receive the feedback signal and to adjust a property of the output light beam in response to the feedback signal. | 09-03-2015 |
20150342016 | TARGET FOR LASER PRODUCED PLASMA EXTREME ULTRAVIOLET LIGHT SOURCE - Techniques for generating EUV light include directing a first pulse of radiation toward a target material droplet to form a modified droplet, the first pulse of radiation having an energy sufficient to alter a shape of the target material droplet; directing a second pulse of radiation toward the modified droplet to form an absorption material, the second pulse of radiation having an energy sufficient to change a property of the modified droplet, the property being related to absorption of radiation; and directing an amplified light beam toward the absorption material, the amplified light beam having an energy sufficient to convert at least a portion of the absorption material into extreme ultraviolet (EUV) light. | 11-26-2015 |
20160007434 | EXTREME ULTRAVIOLET LIGHT SOURCE - An initial pulse of radiation is generated; a section of the initial pulse of radiation is extracted to form a modified pulse of radiation, the modified pulse of radiation including a first portion and a second portion, the first portion being temporally connected to the second portion, and the first portion having a maximum energy that is less than a maximum energy of the second portion; the first portion of the modified pulse of radiation is interacted with a target material to form a modified target; and the second portion of the modified pulse of radiation is interacted with the modified target to generate plasma that emits extreme ultraviolet (EUV) light. | 01-07-2016 |
Patent application number | Description | Published |
20100238572 | DISPLAY DEVICE WITH OPENINGS BETWEEN SUB-PIXELS AND METHOD OF MAKING SAME - An electromechanical systems device includes a plurality of supports disposed over a substrate and a deformable reflective layer disposed over the plurality of supports. The deformable reflective layer includes a plurality of substantially parallel columns extending in a first direction. Each column has one or more slots extending in a second direction generally perpendicular to the first direction. The slots can be created at boundary edges of sub-portions of the columns so as to partially mechanically separate the sub-portions without electrically disconnecting them. A method of fabricating an electromechanical device includes depositing an electrically conductive deformable reflective layer over a substrate, removing one or more portions of the deformable layer to form a plurality of electrically isolated columns, and forming at least one crosswise slot in at least one of the columns. | 09-23-2010 |
20110169724 | INTERFEROMETRIC PIXEL WITH PATTERNED MECHANICAL LAYER - Interferometric modulators and methods of making the same are disclosed. In one embodiment, an interferometric display includes a sub-pixel having a membrane layer with a void formed therein. The void can be configured to increase the flexibility of the membrane layer. The sub-pixel can further include an optical mask configured to hide the void from a viewer. In another embodiment, an interferometric display can include at least two movable reflectors wherein each movable reflector has a different stiffness but each movable reflector has substantially the same effective coefficient of thermal expansion. | 07-14-2011 |
20110235155 | MECHANICAL LAYER AND METHODS OF SHAPING THE SAME - A method of shaping a mechanical layer is disclosed. In one embodiment, the method comprises depositing a support layer, a sacrificial layer and a mechanical layer over a substrate, and forming a support post from the support layer. A kink is formed adjacent to the support post in the mechanical layer. The kink comprises a rising edge and a falling edge, and the kink can be configured to control the shaping and curvature of the mechanical layer upon removal of the sacrificial layer. | 09-29-2011 |
20110249315 | MECHANICAL LAYER AND METHODS OF FORMING THE SAME - This disclosure provides mechanical layers and methods of forming the same. In one aspect, an electromechanical systems device includes a substrate and a mechanical layer having an actuated position and a relaxed position. The mechanical layer is spaced from the substrate to define a collapsible gap. The gap is in a collapsed condition when the mechanical layer is in the actuated position and in a non-collapsed condition when the mechanical layer is in the relaxed position. The mechanical layer includes a reflective layer, a conductive layer, and a supporting layer. The supporting layer is positioned between the reflective layer and the conductive layer and is configured to support the mechanical layer. | 10-13-2011 |
20120056855 | INTERFEROMETRIC DISPLAY DEVICE - This disclosure provides systems, methods, and apparatus including one or more capacitance control layers to decrease the magnitude of an electric field between a movable layer and an electrode. In one aspect, a display device includes an electrode, a movable layer, and a capacitance control layer. At least a portion of the movable layer can be configured to move toward the electrode when a voltage is applied across the electrode and the movable layer and an interferometric cavity can be disposed between the movable layer and the first electrode. The capacitance control layer can be configured to decrease the magnitude of an electric field between the movable layer and the electrode when the voltage is applied across the movable layer and the electrode. | 03-08-2012 |
20120242638 | DIELECTRIC SPACER FOR DISPLAY DEVICES - This disclosure provides systems, methods and apparatus for forming spacers on a substrate and building an electromechanical device over the spacers and the substrate. In one aspect, a raised anchor area is formed over the spacer by adding layers that result in a high point above the substrate. The high point can protect the movable sections of the MEMS device from contact with a backplate. | 09-27-2012 |
20120248478 | PIXEL VIA AND METHODS OF FORMING THE SAME - This disclosure provides systems, methods and apparatuses for pixel vias. In one aspect, a method of forming an electromechanical device having a plurality of pixels includes depositing an electrically conductive black mask on a substrate at each of four corners of each pixel, depositing a dielectric layer over the black mask, depositing an optical stack including a stationary electrode over the dielectric layer, depositing a mechanical layer over the optical stack, and anchoring the mechanical layer over the optical stack at each corner of each pixel. The method further includes providing a conductive via in a first pixel of the plurality of pixels, the via in the dielectric layer electrically connecting the stationary electrode to the black mask, the via disposed at a corner of the first pixel, offset from where the mechanical layer is anchored over the optical stack in an optically non-active area of the first pixel. | 10-04-2012 |
20120249558 | PIXEL VIA AND METHODS OF FORMING THE SAME - This disclosure provides systems, methods and apparatuses for pixel vias. In one aspect, a method of forming an electromechanical device having a plurality of pixels includes depositing an electrically conductive black mask on a substrate at each of four corners and along at least one edge region of each pixel, depositing a dielectric layer over the black mask, depositing an optical stack including a stationary electrode over the dielectric layer, and depositing a mechanical layer over the optical stack. The method further includes providing a conductive via in a first pixel of the plurality of pixels, the via disposed in the dielectric layer and electrically connecting the stationary electrode to the black mask, the via disposed in a position along an edge of the first pixel, spaced offset from the edge of the first pixel in a direction towards the center of the first pixel. | 10-04-2012 |
20130057558 | MECHANICAL LAYER AND METHODS OF MAKING THE SAME - This disclosure provides systems, methods and apparatus for controlling a mechanical layer. In one aspect, an electromechanical systems device includes a substrate and a mechanical layer positioned over the substrate to define a gap. The mechanical layer is movable in the gap between an actuated position and a relaxed position, and includes a mirror layer, a cap layer, and a dielectric layer disposed between the mirror layer and the cap layer. The mechanical layer is configured to have a curvature in a direction away from the substrate when the mechanical layer is in the relaxed position. In some implementations, the mechanical layer can be formed to have a positive stress gradient directed toward the substrate that can direct the curvature of the mechanical layer upward when the sacrificial layer is removed. | 03-07-2013 |
20130088498 | ELECTROMECHANICAL SYSTEMS DEVICE WITH NON-UNIFORM GAP UNDER MOVABLE ELEMENT - Systems, methods and apparatus are provided for electromechanical systems devices having a non-uniform gap under a mechanical layer. An electromechanical systems device includes a movable element supported at its edges over a substrate by at least two support structures. The movable element can be spaced from the substrate by a gap having two or more different heights in two or more corresponding distinct regions. The gap has a first height in a first region below the gap, such as an active area of the device, and a second height in a second region adjacent the support structure. In an interferometric modulator implementation, the second region can be encompasses within an anchor region with a black mask. | 04-11-2013 |
20130100145 | ELECTROMECHANICAL SYSTEMS DEVICE - This disclosure provides systems, methods, and apparatus for EMS devices. In one aspect, an EMS device includes at least one movable layer configured to move relative to one or more electrodes. The at least one movable layer can include a first conductive layer, a second conductive layer, and a non-conductive layer disposed between the first conductive layer and the second conductive layer. In some implementations, the movable layer can include at least one conductive via electrically connecting the first conductive layer and the second conductive layer through the non-conductive layer. | 04-25-2013 |
20130100518 | TUNING MOVABLE LAYER STIFFNESS WITH FEATURES IN THE MOVABLE LAYER - This disclosure provides systems, methods and apparatus for an electromechanical systems device. In one aspect, an electromechanical systems device may include a substrate and a movable layer positioned apart from the substrate. The movable layer and the substrate may define a cavity. The movable layer may be movable to increase the size of the cavity or to decrease the size of the cavity. The movable layer also may include a first anchor point attaching the movable layer to the substrate and a first feature associated with the first anchor point. The first feature may include a protrusion of the movable layer into or out from the cavity. | 04-25-2013 |
20140071139 | IMOD PIXEL ARCHITECTURE FOR IMPROVED FILL FACTOR, FRAME RATE AND STICTION PERFORMANCE - Pixels that include display elements that are configured with different structural dimensions corresponding to the color of light they provide are disclosed. In one implementation, a display device includes an array having a plurality of electromechanical pixels disposed on a substrate, each pixel including at least a first display element and a second display element. Each of the first and second display elements interferometrically modulating light by moving a reflective element between a relaxed position spaced apart from the substrate to an actuated position further away from the substrate than the relaxed position by applying a voltage across the reflective element and a stationary electrode. The stationary electrode of each display element is sized to provide actuation of the movable reflective element using the same actuation voltage even though the electrical gap through which the reflective element moves is different within a pixel. | 03-13-2014 |
20140078185 | SYSTEMS, DEVICES, AND METHODS FOR IMPROVING IMAGE QUALITY OF A DISPLAY - This disclosure provides systems, methods and apparatus for writing data to a display. In one aspect, the display includes an array of display elements arranged at the intersection of a plurality of common lines and segment lines. The display also includes a common driver and a segment driver coupled to the common lines and segment lines. According to one aspect, the display includes a greater number of segment lines than columns of display elements in the array. According to another aspect, the display may also include a first number of display element segment electrodes that are coupled to each other along a first common line, and a second number of display element segment electrodes coupled to each other along a second common line, where the first number is different than the second number. | 03-20-2014 |
20140168223 | PIXEL ACTUATION VOLTAGE TUNING - This disclosure provides systems, methods and apparatus for electromechanical systems displays. In one aspect, the display can include a plurality of electromechanical display elements including a first set of electromechanical display elements and a second set of electromechanical display elements. Each electromechanical display element can include a common electrode and a segment electrode. Each of the segment electrodes of the first set of electromechanical display elements can have a first area located under the common electrodes of the first set. Each of the segment electrodes of the second set of electromechanical display elements can have a second area smaller than the first area located under the common electrodes of the second set. In some implementations, an actuation voltage of each electromechanical display element of the first set is approximately the same as an actuation voltage of each electromechanical display element of the second set. | 06-19-2014 |
20140192060 | CONTROLLING MOVABLE LAYER SHAPE FOR ELECTROMECHANICAL SYSTEMS DEVICES - Systems, methods and apparatus are provided for controlling launch effects of movable layers in electromechanical systems (EMS) devices. First and second EMS devices with first and second step creating layers are positioned over a substrate and spaced, by different gaps, from the movable layers of the EMS devices. The movable layers of the first and second EMS devices include steps having different heights and/or different edge spacing from the center of an anchoring region of each EMS device. The different steps can provide different launch effects for different EMS devices, and if the same thickness of sacrificial material is used for the different devices, the different launch effects can be responsible for different gap heights in the unbiased conditions. | 07-10-2014 |
Patent application number | Description | Published |
20080242624 | Cyclin D Polynucleotides, Polypeptides and Uses Thereof - The invention provides isolated polynucleotides, specifically Cyclin D polynucleotides, and their encoded proteins that are involved in cell cycle regulation. The invention further provides recombinant expression cassettes, host cells, transgenic plants, and antibody compositions. The present invention provides methods and compositions relating to altering cell cycle protein content and/or composition of plants for the purpose of increasing transformation efficiency. | 10-02-2008 |
20090133152 | METHODS FOR ALTERING THE GENOME OF A MONOCOT PLANT CELL - Methods and compositions for altering the genome of a monocot plant cell, and a monocot plant are disclosed. The methods and compositions use a double-strand break inducing agent to alter a monocot plant or plant cell genomic sequence comprising a recognition sequence for the double-strand break inducing agent. | 05-21-2009 |
20100100981 | WUSCHEL (WUS) GENE HOMOLOGS - This invention relates to isolated polynucleotides encoding WUS polypeptides. The invention further provides isolated WUS polypeptides. The invention also provides methods of using the polynucleotides to modulate the level of WUS, improve transformation efficiency, to stimulate plant cell growth, including stem cells, to stimulate organogenesis, to stimulate somatic embryogenesis, to induce apomixis, and to provide a positive selection for cells comprising the polynucleotide. The invention also relates to cells, plants and seeds comprising the polynucleotides of the invention or produced by the methods of the invention. | 04-22-2010 |
20100285591 | CYCLIN D POLYNUCLEOTIDES, POLYPEPTIDES AND USES THEREOF - The invention provides isolated polynucleotides, specifically Cyclin D polynucleotides, and their encoded proteins that are involved in cell cycle regulation. The invention further provides recombinant expression cassettes, host cells, transgenic plants, and antibody compositions. The present invention provides methods and compositions relating to altering cell cycle protein content and/or composition of plants for the purpose of increasing transformation efficiency. | 11-11-2010 |
20110167522 | CYCLIN D POLYNUCLEOTIDES, POLYPEPTIDES AND USES THEREOF - The invention provides isolated polynucleotides, specifically Cyclin D polynucleotides, and their encoded proteins that are involved in cell cycle regulation. The invention further provides recombinant expression cassettes, host cells, transgenic plants, and antibody compositions. The present invention provides methods and compositions relating to altering cell cycle protein content and/or composition of plants for the purpose of increasing transformation efficiency. | 07-07-2011 |
20130139279 | WUSCHEL (WUS) GENE HOMOLOGS - This invention relates to isolated polynucleotides encoding WUS polypeptides. The invention further provides isolated WUS polypeptides. The invention also provides methods of using the polynucleotides to modulate the level of WUS, improve transformation efficiency, to stimulate plant cell growth, including stem cells, to stimulate organogenesis, to stimulate somatic embryogenesis, to induce apomixis, and to provide a positive selection for cells comprising the polynucleotide. The invention also relates to cells, plants and seeds comprising the polynucleotides of the invention or produced by the methods of the invention. | 05-30-2013 |
20140287419 | Compositions Having Dicamba Decarboxylase Activity and Methods of Use - Compositions and methods comprising polynucleotides and polypeptides having dicamba decarboxylase activity are provided. Further provided are nucleic acid constructs, host cells, plants, plant cells, explants, seeds and grain having the dicamba decarboxylase sequences. Various methods of employing the dicamba decarboxylase sequences are provided. Such methods include, for example, methods for decarboxylating an auxin-analog, method for producing an auxin-analog tolerant plant, plant cell, explant or seed and methods of controlling weeds in a field containing a crop employing the plants and/or seeds disclosed herein. Methods are also provided to identify additional dicamba decarboxylase variants. | 09-25-2014 |
20140289906 | Compositions Having Dicamba Decarboxylase Activity and Methods of Use - Compositions and methods comprising polynucleotides and polypeptides having dicamba decarboxylase activity are provided. Further provided are nucleic acid constructs, host cells, plants, plant cells, explants, seeds and grain having the dicamba decarboxylase sequences. Various methods of employing the dicamba decarboxylase sequences are provided. Such methods include, for example, methods for decarboxylating an auxin-analog, method for producing an auxin-analog tolerant plant, plant cell, explant or seed and methods of controlling weeds in a field containing a crop employing the plants and/or seeds disclosed herein. Methods are also provided to identify additional dicamba decarboxylase variants. | 09-25-2014 |
20150074843 | Methods For Altering The Genome Of A Monocot Plant Cell - Methods and compositions for altering the genome of a monocot plant cell, and a monocot plant are disclosed. The methods and compositions use a double-strand break inducing agent to alter a monocot plant or plant cell genomic sequence comprising a recognition sequence for the double-strand break inducing agent. | 03-12-2015 |
20150351390 | COMPOSITIONS AND METHODS FOR AUXIN-ANALOG CONJUGATION - Compositions and methods are provided to detoxify an auxin-analog herbicide through the use of at least one GH3 polypeptide having amino acid/auxin analog herbicide conjugation activity. Such GH3 polypeptides in the presence of an auxin-analog herbicide will produce an amino acid/auxin-analog conjugate having reduced herbicidal activity. | 12-10-2015 |