Patent application number | Description | Published |
20090038142 | METHODS OF FORMING INDUCTORS ON INTEGRATED CIRCUITS - The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. In some embodiments, at least one core element of the second set of core elements is positioned in a space between an associated adjacent pair of core elements from the first set of core elements. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the forming of a metal seed layer, the deposition and patterning of photoresist, the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements. | 02-12-2009 |
20090040000 | INTEGRATED CIRCUITS WITH INDUCTORS - The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways. Particular embodiments involve core elements having different compositions and/or sizes. | 02-12-2009 |
20090094818 | Magnetically enhanced power inductor with self-aligned hard axis magnetic core produced using a damascene process sequence - A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis can be enhanced by electroplating in an applied magnetic field parallel to the easy axis. | 04-16-2009 |
20090256236 | MEMS-topped integrated circuit with a stress relief layer and method of forming the circuit - The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices. | 10-15-2009 |
20090256667 | MEMS power inductor and method of forming the MEMS power inductor - A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace. | 10-15-2009 |
20100068864 | APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS - Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils. | 03-18-2010 |
20100079929 | CMOS COMPATIBLE INTEGRATED HIGH DENSITY CAPACITOR STRUCTURE AND PROCESS SEQUENCE - Integrated circuits structures and process sequences are provided for forming CMOS compatible high-density capacitors. The anodization of tantalum to tantalum oxide in the formation of the inter-plate capacitor dielectric results in very high dielectric constants since the defects usually found in the inter-plate dielectric are eliminated in the volume expansion that occurs during the oxidation of the tantalum material. This permits the fabrication of larger capacitors that can be incorporated into standard CMOS process flows. | 04-01-2010 |
20100190311 | Method of Forming a MEMS Topped Integrated Circuit with a Stress Relief Layer - The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices. | 07-29-2010 |
20100213601 | INTEGRATED CIRCUIT MICRO-MODULE - In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer or electrically conductive vias. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, interconnect layers, conductive vias that electrically connect different components of the package and/or passive devices. In some specific embodiments, the dielectric layers are formed from a suitable epoxy such as SU-8 type. In a method aspect of the invention, the dielectric layers may be formed using a spin-on coating approach and patterned using conventional photolithographic techniques. | 08-26-2010 |
20100213602 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed. The integrated circuit is electrically connected to the external package contacts at least partly through one or more of the conductive interconnect layers. Various embodiments pertain to apparatuses that are formed by performing some or all of the aforementioned operations. | 08-26-2010 |
20100213603 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit. | 08-26-2010 |
20100213604 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described. | 08-26-2010 |
20100213607 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple Microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the Microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate. Molding material is applied over the top surface of the substrate and the Microsystems to form a molded structure. Portions of the substrate can be removed. The molded structure can be singulated to form individual integrated circuit packages. Each of the integrated circuit packages contains at least one microsystem. Various embodiments involve forming conductive pads on the top surface of the substrate instead of the metal vias. | 08-26-2010 |
20100216280 | INTEGRATED CIRCUIT MICRO-MODULE - Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed. The integrated circuit is electrically connected with the external package contacts at least in part through one or more of the conductive interconnect layers. | 08-26-2010 |
20100295638 | METHOD OF SWITCHING A MAGNETIC MEMS SWITCH - A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators. | 11-25-2010 |
20110025443 | APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS - An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure. | 02-03-2011 |
20110095365 | Power transistor with improved high-side operating characteristics and reduced resistance and related apparatus and method - A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device. | 04-28-2011 |
20110115071 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit. | 05-19-2011 |
20110250730 | Method of Forming High Capacitance Semiconductor Capacitors with a Single Lithography Step - An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer. | 10-13-2011 |
20110260248 | SOI Wafer and Method of Forming the SOI Wafer with Through the Wafer Contacts and Trench Based Interconnect Structures that Electrically Connect the Through the Wafer Contacts - A silicon-on-insulator (SOI) wafer is formed to have through-the-wafer contacts, and trench based interconnect structures on the back side of the SOI wafer that electrically connect the through-the-wafer contacts. In addition, selected ones of the through-the-wafer contacts bias the bodies of the MOS transistors. | 10-27-2011 |
20120009689 | Method of Forming a MEMS Power Inductor - A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace. | 01-12-2012 |
20120161294 | Method of Batch Trimming Circuit Elements - Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit. | 06-28-2012 |
20120187508 | INTEGRATION OF STRUCTURALLY-STABLE ISOLATED CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER (CMUT) ARRAY CELLS AND ARRAY ELEMENTS - A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer. | 07-26-2012 |
20120200377 | MEMS Relay and Method of Forming the MEMS Relay - A micro-electromechanical systems (MEMS) relay includes a switch with a first contact region and a second contact region that are vertically separated from each other by a gap. The MEMS relay requires a small vertical movement to close the gap and therefore is mechanically robust. In addition, the MEMS relay has a small footprint and, therefore, can be formed on top of small integrated circuits. | 08-09-2012 |
20120217610 | Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections - A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding. | 08-30-2012 |
20120233849 | MAGNETICALLY ENHANCED POWER INDUCTOR WITH SELF-ALIGNED HARD AXIS MAGNETIC CORE PRODUCED IN AN APPLIED MAGNETIC FIELD USING A DAMASCENE PROCESS SEQUENCE - A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis. | 09-20-2012 |
20120280781 | METHOD OF MAKING A CONTROLLED SEAM LAMINATED MAGNETIC CORE FOR HIGH FREQUENCY ON-CHIP POWER INDUCTORS - A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween. | 11-08-2012 |
20130043970 | METHOD AND APPARATUS FOR ACHIEVING GALVANIC ISOLATION IN PACKAGE HAVING INTEGRAL ISOLATION MEDIUM - An inductor device having an improved galvanic isolation layer arranged between a pair of coil and methods of its construction are described. | 02-21-2013 |
20130049916 | SEMICONDUCTOR STRUCTURE WITH GALVANICALLY-ISOLATED SIGNAL AND POWER PATHS - A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die. | 02-28-2013 |
20130122628 | MEMS Relay and Method of Forming the MEMS Relay - A micro-electromechanical systems (MEMS) relay includes a switch with a first contact region and a second contact region that are vertically separated from each other by a gap. The MEMS relay requires a small vertical movement to close the gap and therefore is mechanically robust. In addition, the MEMS relay has a small footprint and, therefore, can be formed on top of small integrated circuits. | 05-16-2013 |
20130140654 | Low Frequency CMUT with Vent Holes - A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. | 06-06-2013 |
20130140704 | Low Frequency CMUT with Thick Oxide - A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, utilizes a thick oxide layer to substantially increase the volume of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. In addition, the CMUT can include a back side bond pad structure that eliminates the need for and cost of one patterned photoresist layer. | 06-06-2013 |
20130200474 | Low Frequency CMUT with Vent Holes - A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. | 08-08-2013 |
20130249023 | High Frequency CMUT - A high-frequency capacitive micromachined ultrasonic transducer (CMUT) has a silicon membrane and an overlying metal silicide layer that together form a conductive structure which can vibrate over a cavity. The CMUT also has a metal structure that touches a group of conductive structures. The metal structure has an opening that extends completely through the metal structure to expose the conductive structure. | 09-26-2013 |