Patent application number | Description | Published |
20130164674 | NOVEL ACRYL MONOMER, POLYMER AND RESIST COMPOSITION COMPRISING SAME - Disclosed are an acrylic monomer having a structure represented by formula (1), a polymer containing a repeating unit derived from the acrylic monomer, and a resist composition prepared by using the polymer, which exhibits excellent adhesiveness, storage stability, and enhanced line width roughness, exhibits excellent resolution in both C/H patterns and L/S patterns, has an excellent process window so that an excellent pattern profile can be obtained regardless of the type of the substrate, and exhibits improved contrast. | 06-27-2013 |
20130171560 | ADDITIVE FOR RESIST AND RESIST COMPOSITION COMPRISING SAME - Provided are an additive for resist represented by the following formula (1), and a resist composition containing the additive. The additive according to the present invention can suppress leaching caused by water during an immersion lithographic process by increasing hydrophobicity of the surface of the resist film in the exposure at the time of applying the additive to a resist composition, and can form a fine resist pattern having excellent sensitivity and resolution at the time of applying the additive to a resist composition. | 07-04-2013 |
20130171561 | ADDITIVE FOR RESIST AND RESIST COMPOSITION COMPRISING SAME - A resist additive represented by Formula 1 below and a resist composition including the additive are disclosed. The resist additive improves hydrophobicity of the surface of the resist film to prevent materials from being leached in water during exposure of immersion lithography and is converted to have hydrophilicity by deprotection reaction during development. As a result, a micropattern of a resist film with excellent sensitivity and high resolution is formed. | 07-04-2013 |
Patent application number | Description | Published |
20120123078 | METALLOCENE COMPOUND, CATALYST COMPOSITION COMPRISING THE SAME, AND AN OLEFINIC POLYMER PRODUCED USING THE SAME - The present invention relates to a novel metallocene compound, a catalyst composition comprising the same, and to olefinic polymers produced using the same. The metallocene compound according to the present invention and the catalyst composition comprising the same can be used when producing olefinic polymers, have outstanding copolymerisation properties, and can produce olefinic polymers of high molecular weight. In particular, when the metallocene compound according to the present invention is employed, highly heat resistant block copolymers can be produced, and olefinic polymers can be produced which have a high melting point (Tm) even if the comonomer content is increased when producing the olefinic polymer. | 05-17-2012 |
20140066288 | METALLOCENE COMPOUND, CATALYST COMPOSITION COMPRISING THE SAME, AND AN OLEFINIC POLYMER PRODUCED USING THE SAME - The present invention relates to a novel metallocene compound, a catalyst composition comprising the same, and to olefinic polymers produced using the same. The metallocene compound according to the present invention and the catalyst composition comprising the same can be used when producing olefinic polymers, have outstanding copolymerisation properties, and can produce olefinic polymers of high molecular weight. In particular, when the metallocene compound according to the present invention is employed, highly heat resistant block copolymers can be produced, and olefinic polymers can be produced which have a high melting point (Tm) even if the comonomer content is increased when producing the olefinic polymer. | 03-06-2014 |
20140094574 | POLYOLEFIN AND PREPARATION METHOD THEREOF - A polyolefin has 1) a density in the range of 0.93 to 0.97 g/cm | 04-03-2014 |
Patent application number | Description | Published |
20130065152 | CHANNEL PLATE ASSEMBLY OF STACK FOR FUEL CELL AND METHOD OF MANUFACTURING CHANNEL PLATE ASSEMBLY - A channel plate assembly of a stack for a fuel cell and a method of manufacturing the channel plate assembly. The channel plate assembly of a stack for a fuel cell includes a bridge piece disposed on a channel plate to entirely surround a manifold, and a gasket disposed on the channel plate to cover the bridge piece, wherein the channel plate assembly is manufactured in an integrated fashion. | 03-14-2013 |
20140178788 | CATALYST SLURRY FOR FUEL CELL, ELECTRODE PREPARED USING THE SAME, MEMBRANE-ELECTRODE ASSEMBLY INCLUDING THE ELECTRODE, FUEL CELL INCLUDING THE MEMBRANE-ELECTRODE ASSEMBLY, AND METHOD OF PREPARING THE ELECTRODE - A catalyst slurry for a fuel cell, an electrode manufactured using the catalyst slurry, a membrane-electrode assembly including the electrode, a fuel cell including the membrane-electrode assembly, and a method of manufacturing the electrode are provided. The catalyst slurry includes a catalyst material, an acid component, a binder, and a solvent component having a viscosity of at least about 20 cps at about 20° C. | 06-26-2014 |
20150050576 | FUEL CELL SYSTEM AND METHOD OF CONTROLLING CONCENTRATION OF FUEL - A method of controlling a concentration of a fuel to be supplied to a stack of a fuel cell system, the method including determining a reference concentration of the fuel to be supplied to the stack when the stack is in a normal mode, monitoring temperature of the stack, and controlling the concentration of the fuel to be supplied to the stack, based on a result of the monitoring the temperature of the stack. | 02-19-2015 |
20150111124 | CATALYST SLURRY FOR FUEL CELL, AND ELECTRODE, MEMBRANE ELECTRODE ASSEMBLY AND FUEL CELL USING THE SAME - A catalyst slurry including a catalyst material, a polymer binder, a plurality of inorganic particles, wherein each particle includes an ionic group, a hydrophilic oligomer, and a solvent. | 04-23-2015 |
20150261176 | CARTRIDGE AND ELECTROPHOTOGRAPHIC IMAGE FORMING APPARATUS USING THE SAME - A cartridge is attached to or detached from a main body of an image forming apparatus that has an opening portion and a door that opens or closes the opening portion. The cartridge includes: a memory unit with a contact portion via which the cartridge is connected to the main body to transmit information of the cartridge to the main body; and a moving member on which the contact portion is mounted, wherein the moving member is moved to a first position where the contact portion is hidden inside the cartridge and a second position where the contact portion protrudes out of the cartridge to be connected to a connection portion provided in the main body, the moving member being moved to the second position in connection with closing of the door. | 09-17-2015 |
20150261177 | CARTRIDGE AND ELECTROPHOTOGRAPHIC IMAGE FORMING APPARATUS USING THE SAME - A cartridge that is attached to or detached from a main body of an image forming apparatus, including: a memory unit that includes a contact portion via which the cartridge is connected to the main body and that is connected to the main body to transmit information of the cartridge to the main body; and a moving member on which the contact portion is mounted, wherein the moving unit is moved to a second position where the contact portion is protruded out of the cartridge in order to be connected to a connection portion provided in the main body and a first position that is hidden inside the cartridge. | 09-17-2015 |
Patent application number | Description | Published |
20090072322 | SEMICONDUCTOR DEVICES INCLUDING LINE PATTERNS SEPARATED BY CUTTING REGIONS - Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and which are separated from each other by at least one cutting region therebetween. The dummy line patterns can include first and second dummy line patterns which are adjacent to each other in a second direction that is perpendicular to the first direction. At least one of the cutting regions between a pair of sub-line patterns of the first dummy line pattern is aligned with and bounded by one of the sub-line patterns of the second dummy line pattern in the second direction. | 03-19-2009 |
20100207690 | METHOD OF APPLYING WIRE VOLTAGE TO SEMICONDUCTOR DEVICE - A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented. | 08-19-2010 |
20120142177 | METHODS OF MANUFACTURING A WIRING STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a wiring structure and a semiconductor device, the method of manufacturing a wiring structure including forming a first insulating interlayer on a substrate; forming a contact plug in an opening in the first insulating interlayer; forming a second insulating interlayer on the contact plug and the first insulating interlayer; removing a portion of the second insulating interlayer to form an opening therethrough such that the opening exposes the contact plug; filling a portion of the opening to form a wiring such that the wiring is electrically connected to the contact plug; and forming a diffusion barrier layer pattern on the wiring such that the diffusion barrier layer pattern fills a remaining portion of the opening. | 06-07-2012 |
20120318567 | WIRING STRUCTURES - A wiring structure includes a first plug extending through a first insulating interlayer on a substrate, a first wiring extending through a second insulating interlayer on the first insulating interlayer and the first wiring is electrically connected to the first plug, a diffusion barrier layer pattern on the first wiring and on the second insulating interlayer, a portion of the second insulating interlayer being free of being covered by the diffusion barrier layer pattern, a second plug extending through the diffusion barrier layer pattern, the second plug is in contact with the first wiring, and a second wiring electrically connected to the second plug. | 12-20-2012 |
20130032871 | SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD OF FABRICATING THE SAME - A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench. | 02-07-2013 |
20130214413 | CONDUCTIVE LINE STRUCTURES AND METHODS OF FORMING THE SAME - Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns. | 08-22-2013 |
20140284695 | VERTICAL CELL-TYPE SEMICONDUCTOR DEVICE HAVING PROTECTIVE PATTERN - According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer. | 09-25-2014 |
20150061132 | CONDUCTIVE LINE STRUCTURES AND METHODS OF FORMING THE SAME - Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns. | 03-05-2015 |
20150137216 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend. | 05-21-2015 |
20150318296 | NON-VOLATILE MEMORY DEVICES WITH VERTICALLY INTEGRATED CAPACITOR ELECTRODES - Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes. | 11-05-2015 |
20150340374 | MEMORY DEVICE - A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer. | 11-26-2015 |
20150348987 | SEMICONDUCTOR DEVICE INCLUDING DIFFERENT ORIENTATIONS OF MEMORY CELL ARRAY AND PERIPHERAL CIRCUIT TRANSISTORS - A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease. | 12-03-2015 |
20160093631 | MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure. The isolation insulating layer divides at least one of the conductive electrode layers in the stack structure into electrically separate portions. | 03-31-2016 |
Patent application number | Description | Published |
20080237679 | SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS AND METHODS OF FABRICATING THE SAME - A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern. | 10-02-2008 |
20080268218 | INSULATED ELECTRIC WIRE - The present invention relates to an insulated electric wire. The insulated electric wire according to the present invention includes a high adhesion resin layer made of a polyamideimide resin containing a compound having a polar group in a molecular structure of an insulation material; and a high flexibility resin layer provided on the high adhesion resin layer. The present invention advantageously improves adherence between a polyamideimide resin and a conductor, and provides adhesive strength with the conductor to improve flexibility of the insulated electric wire and at the same time to improve flexibility of an insulator without deterioration of heat resistance of the insulator. | 10-30-2008 |
20090202830 | ENAMEL VARNISH COMPOSITION FOR ENAMEL WIRE AND ENAMEL WIRE USING SAME - Disclosed are enamel varnish compositions for an enamel wire and an enamel wire using the same. The present invention relates to enamel varnish compositions for an enamel wire in which a polymeric resin component is included in an organic solvent, wherein the polymeric resin component includes a first polyamideimide resin; and a second resin having polyamideimide in which a triazine ring is introduced into a major chain. The enamel wire, in which such a coating pigment composition is applied to the innermost layer, has the increased adhesivity of the insulated coating layer to the conducting wire, as well as the excellent physical properties such as the wear resistance and flexibility, etc. | 08-13-2009 |
20110217835 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS - A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern. | 09-08-2011 |