Patent application number | Description | Published |
20090134856 | Method of optimum current blanking time implementation in current sense circuit - In a method and system for sensing current in a switching regulator (SWR) operating in a current mode, a power switch is coupled to receive the current from a switching element, the power switch being controlled by a gate signal. An inrush of the current causes an initial transient spike (ITS). A buffer having a buffer input and a buffer output is coupled to receive the gate signal and provide a buffered gate signal. The buffer output is disabled during the ITS. A sense switch (SW) is coupled to receive a portion of the current from the switching element, the SW being turned on by the buffered gate signal after the initial transient spike. A sense resistor (SR) is coupled to receive the portion of the current from the SW. An amplifier converts the portion of the current through the SR to a voltage signal for controlling the SWR. | 05-28-2009 |
20090189669 | METHODS AND APPARATUS TO REDUCE PROPAGATION DELAY OF CIRCUITS - Methods and apparatus to reduce propagation delay of circuits are disclosed. A disclosed apparatus to reduce propagation delay of a circuit comprises a level shifter to selectively turn a first circuit on and off; a first switch to couple the first circuit to a second circuit when the first circuit is on, wherein the second circuit is to selectively receive a first current from the first circuit based on a signal the second circuit receives from the level shifter; and a second switch to couple the first circuit to a reference signal based on the first current, the second switch causing the first circuit to start to turn off. | 07-30-2009 |
20100164528 | Methods and Apparatus to Test Electronic Devices - Methods and apparatus to test electronic devices are disclosed. An example method includes setting a first controlled switch to prevent a current detect signal from tripping an overcurrent protection event controlling an operation of the device; setting a second controlled switch to route a first sensed voltage associated with the device to a voltage adjuster; sending a calibration current corresponding to a target threshold current through the device; detecting the first sensed voltage while the calibration current flows through the device; and setting a reference signal substantially equal to the first sensed voltage, wherein the reference signal is to be used to generate the current detect signal. | 07-01-2010 |
20100327777 | CLAMP TO ENABLE LOW VOLTAGE SWITCHING FOR HIGH VOLTAGE TERMINAL APPLICATIONS - An output stage for an LED driver is provided. In particular, a low voltage clamp, which uses several cascode circuits, is provided to protect low voltage switching transistors in the range of two times higher voltage application under both normal and fault conditions. Additionally, a circuit for regulating the bias voltage applied to each of the cascode circuits is provided to prevent damage during startup, while an internal voltage regulator is settling. | 12-30-2010 |
20100327928 | METHOD AND APPARATUS TO IMPROVE AND CONTROL THE PROPAGATION DELAY IN A CURRENT SLEWING CIRCUIT - A circuit for independently controlling slew and propagation delay of a current DAC is provided. The circuit applies dual slope technique with feed-back control the gate (or control electrode) of a switching transistor to make propagation delay independent control from rise/fall slew rate. This allows one to adjust propagation delay and current slew rate separately to achieve better performance. | 12-30-2010 |
20110278936 | LOW DROPOUT REGULATOR WITH MULTIPLEXED POWER SUPPLIES - Generally, with low drop out (LDO) regulators that use multiplexed power supplies, the transistors within the regulator can use a substantial amount of area. Here, a regulator is provided that uses a multiplexer to commonly control the back-gates of multiple power transistors within the LDO. By doing this, the area overhead that would normally be present with these switches (of the multiplexer) can be dramatically reduced without sacrificing performance. | 11-17-2011 |
20130015867 | TOUCH SENSING METHOD AND APPARATUSAANM Aras; SualpAACI DallasAAST TXAACO USAAGP Aras; Sualp Dallas TX USAANM Nihei; TatsuyukiAACI TokyoAACO JPAAGP Nihei; Tatsuyuki Tokyo JPAANM Rahman; AbidurAACI AllenAAST TXAACO USAAGP Rahman; Abidur Allen TX US - A method for measuring for generating a touch capacitance measurement is provided. Gain and offset control signals are generated, where the gain and offset control signals are adjusted to compensate for base capacitance of a touch sensor. The gain control signal is applied to a touch sensor during a first phase of a clock signal, and the offset control signal is applied to an output circuit during a second phase of the clock signal. The output circuit is coupled to the touch sensor during the second phase of the clock signal. The touch capacitance measurement is generated by compensating for the base capacitance with the gain and offset control signals, and a gain is applied to the touch capacitance measurement. | 01-17-2013 |
20130169462 | Apparatus and Method for Dynamically Dampening a Transient Step Response - A circuit has a digital to analog (DA) resistance ladder having an analog output; a capacitor coupled to the analog output; a first resistance coupled from the capacitor to ground; and a switch coupled to the capacitor in parallel to the resistor, wherein the switch, when closed, has a second resistance, and the first resistance is greater than the second resistance. | 07-04-2013 |
20130176155 | APPARATUS AND SYSTEM TO SUPPRESS ANALOG FRONT END NOISE INTRODUCED BY CHARGE-PUMP THROUGH EMPLOYMENT OF CHARGE-PUMP SKIPPING - An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal, wherein if the clock for the charge pump is running faster than an analog front end (“AFE”) video sampling clock, a state-machine control is configured to: skip the charge pump clock period right before a video sample signal falling edge, thereby recovering to a normal operation the next charge-pump clock period, wherein this duty cycle modulation of charge pump clock will not substantially impact charge pump output. | 07-11-2013 |
20140254235 | POWER SUPPLY BROWNOUT PROTECTION CIRCUIT AND METHOD FOR EMBEDDED FRAM - Corruption of data in a FRAM ( | 09-11-2014 |
Patent application number | Description | Published |
20090135883 | Multi-Layered Thermal Sensor for Integrated Circuits and Other Layered Structures - A compact resistive thermal sensor is provided for an integrated circuit (IC), wherein different sensor components are placed on different layers of the IC. This allows the lateral area needed for the sensor resistance wire on any particular IC layer to be selectively reduced. In a useful embodiment, a plurality of first linear conductive members are positioned in a first IC layer, in spaced-apart parallel relationship with one another. A plurality of second linear conductive members are similarly positioned in a second IC layer in spaced-apart parallel relationship with one another, and in orthogonal relationship with the first linear members or in parallel with existing wiring channels of the second IC layer. Conductive elements respectively connect the first linear members into a first conductive path, and the second linear members into a second conductive path. A third conductive element extending between the first and second layers connects the first and second conductive paths into a single continuous conductive path, wherein the path has a resistance that varies with temperature. A device responsive to an electric current sent through the continuous path determines temperature of the path from the path resistance. Two or more of the thermal sensors could be connected in series, for use in measuring critical IC circuits. | 05-28-2009 |
20110176579 | MULTI-LAYERED THERMAL SENSOR FOR INTEGRATED CIRCUITS AND OTHER LAYERED STRUCTURES - A compact resistive thermal sensor is provided for an integrated circuit (IC), wherein different sensor components are placed on different layers of the IC. This allows the lateral area needed for the sensor resistance wire on any particular IC layer to be selectively reduced. In a useful embodiment, first linear conductive members are positioned in a first IC layer, in parallel relationship with one another. Second linear conductive members are positioned in a second IC layer in parallel relationship with one another. Conductive elements connect the first linear members into a first conductive path, and the second linear members into a second conductive path. A third conductive element extending between the first and second layers connects the first and second conductive paths into a single conductive path, wherein the path resistance varies with temperature. The path resistance is used to determine temperature. | 07-21-2011 |
20150032786 | IDENTIFICATION OF THE BIT POSITION OF A SELECTED INSTANCE OF A PARTICULAR BIT VALUE IN A BINARY BIT STRING - A circuit for identifying one or more bit positions of instances of a selected bit value in an N-bit input bit string includes a plurality of adders that compute, in parallel, sums of bits in each of P input substrings comprising the input bit string. A plurality of zero position detectors detect, for each of the P input substrings for which a corresponding sum differs from a threshold sum, one or more bit positions of the selected bit value. Correction logic generates adjustment indications indicative of a number of detected instances of the selected bit value. A plurality of output substring adjusters that, based on the detected bit positions and the adjustment indications, collectively output one or more output vectors identifying a bit position of at least an Mth instance of the selected bit value in the input bit string. | 01-29-2015 |
Patent application number | Description | Published |
20130082314 | LOW RESISTANCE STACKED ANNULAR CONTACT - An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components. | 04-04-2013 |
20140131781 | LOW RESISTANCE STACKED ANNULAR CONTACT - An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components. | 05-15-2014 |
Patent application number | Description | Published |
20140301492 | PRECODING MATRIX CODEBOOK DESIGN FOR ADVANCED WIRELESS COMMUNICATIONS SYSTEMS - Methods and apparatus of constructing rank-1 and/or rank-2 codebooks for advanced communication systems with 4 transmit antennas and two-dimensional (2D) M×N transmit antenna elements are provided. A double-codebook structure is considered for 4-Tx antenna configuration. Single-codebook and double-codebook structures are considered for two-dimensional (2D) M×N transmit antenna elements. | 10-09-2014 |
20140341310 | METHODS FOR LINEAR RF BEAM SEARCH IN MILLIMETER WAVE COMMUNICATION SYSTEM WITH HYBRID BEAM-FORMING - Embodiments provide a system, an apparatus, or a method for communicating in a wireless network with a plurality of transmitter radio frequency (RF) chains and a plurality of receiver RF chains. The method includes identifying a set of measurements of a channel for a plurality of transmit and receive beams from the plurality of transmitter and receiver RF chains. The method also includes separating the plurality of transmitter and receiver RF chains into a first subset and a second subset. The method also includes initializing at least one beam to all transmitter RF chains and at least one beam to all receiver RF chains in the first subset. The method also includes identifying at least one selected beam of the plurality of transmit beams to all transmitter RF chains and at least one beam of the plurality of receive beams to all receiver RF chains in the second subset. | 11-20-2014 |
20150263796 | CHANNEL STATE INFORMATION FOR REPORTING AN ADVANCED WIRELESS COMMUNICATIONS SYSTEM - Multi-user channel quality, information (MU-CQI) indicating demodulation interference at the user equipment between co-channel signals within a multi-user, multiple input multiple output (MU-MIMO) transmission is derived utilizing a demodulation interference measurement resource (DM-IMR) and based upon a demodulation reference signal (DMRS). Derivation of signal, interference, and signal-plus-interference parts of the MU-CQI is configurable, as is the MU-CQI reporting, selection of physical resource blocks (PRBs) to be employed, and periods, subframes and/or antenna ports for determining MU-CQI. The interfering transmission may originate from the same transmission point as the desired signal or from a different transmission point. | 09-17-2015 |
20150288499 | PERIODIC AND APERIODIC CHANNEL STATE INFORMATION REPORTING FOR ADVANCED WIRELESS COMMUNICATION SYSTEMS - User equipment and a method for a transceiver operable to communicate with the at least one base station. The processing circuitry configured to control the transceiver to receive a first set of CSI-RS according to a first CSI process configuration; receive a second set of CSI-RS according to a second CSI process configuration; transmit a PUCCH comprising a first RI on a RI reporting subframe derived according to the first CSI process configuration, wherein the first RI is derived using recent channel estimates; and transmit a second PUCCH comprising a channel quality indicator (CQI) and a first PMI on a CQI/PMI reporting subframe derived according to the first CSI process configuration, wherein the CQI and the first PMI are derived using (i) the recent channel estimates, (ii) recent interference estimates, (iii) a second RI, and (iv) at least one of a third RI and a second PMI. | 10-08-2015 |
20150372728 | OFDM SIGNAL COMPRESSION - Methods and apparatuses for fronthaul signal compression and decompression. An apparatus for fronthaul signal compression includes a receiver, signal processing circuitry, and a fronthaul interface. The receiver is configured to receive one or more signals comprising complex samples. The signal processing circuitry is configured to construct vectors representing at least a portion of the complex samples; map the vectors to codeword indices in a vector quantization codebook; and process the codeword indices into an output signal. The fronthaul interface is configured to transmit the output signal via a fronthaul communication link of a wireless network. The vectors may be constructed according to the selected vectorization method. The vector quantization codebook may be selected from a set of vector quantization codebooks generated based on training signals and signaled. | 12-24-2015 |
Patent application number | Description | Published |
20120253680 | Method and System for Passive Electroseismic Surveying - A method of passive surveying comprises generating one or more detected signals by passively detecting a signal generated within a subsurface earth formation due to a seismoelectric response or an electroseismic response in at least one porous subsurface earth formation containing at least one fluid, and processing the one or more detected signals to determine at least one property of the subsurface earth formation. | 10-04-2012 |
20130066561 | Method and System for Passive Electroseismic Surveying - A method of passive surveying comprises generating one or more detected signals by passively detecting a signal generated within a subsurface earth formation due to a seismoelectric response or an electroseismic response in at least one porous subsurface earth formation containing at least one fluid, and processing the one or more detected signals to determine at least one property of the subsurface earth formation. | 03-14-2013 |
20130069654 | Method and System for Passive Electroseismic Surveying - A method of passive surveying comprises generating one or more detected signals by passively detecting a signal generated within a subsurface earth formation due to a seismoelectric response or an electroseismic response in at least one porous subsurface earth formation containing at least one fluid, and processing the one or more detected signals to determine at least one property of the subsurface earth formation. | 03-21-2013 |
20130070562 | Method and System for Passive Electroseismic Surveying - A method of passive surveying comprises generating one or more detected signals by passively detecting a signal generated within a subsurface earth formation due to a seismoelectric response or an electroseismic response in at least one porous subsurface earth formation containing at least one fluid, and processing the one or more detected signals to determine at least one property of the subsurface earth formation. | 03-21-2013 |
20130073210 | Method and System for Passive Electroseismic Surveying - A method of passive surveying comprises generating one or more detected signals by passively detecting a signal generated within a subsurface earth formation due to a seismoelectric response or an electroseismic response in at least one porous subsurface earth formation containing at least one fluid, and processing the one or more detected signals to determine at least one property of the subsurface earth formation. | 03-21-2013 |
20130119993 | METHOD AND SYSTEM FOR PASSIVE ELECTROSEISMIC SURVEYING - A method of passive surveying comprises generating one or more detected signals by passively detecting a signal generated within a subsurface earth formation due to a seismoelectric response or an electroseismic response in at least one porous subsurface earth formation containing at least one fluid, and processing the one or more detected signals to determine at least one property of the subsurface earth formation. | 05-16-2013 |
20130133880 | METHOD AND SYSTEM FOR PASSIVE ELECTROSEISMIC SURVEYING - A method of passive surveying comprises generating one or more detected signals by passively detecting a signal generated within a subsurface earth formation due to a seismoelectric response or an electroseismic response in at least one porous subsurface earth formation containing at least one fluid, and processing the one or more detected signals to determine at least one property of the subsurface earth formation. | 05-30-2013 |
20140039796 | Method and System for Passive Electroseismic Surveying - A method of passive surveying comprises generating one or more detected signals by passively detecting a signal generated within a subsurface earth formation due to a seismoelectric response or an electroseismic response in at least one porous subsurface earth formation containing at least one fluid, and processing the one or more detected signals to determine at least one property of the subsurface earth formation. | 02-06-2014 |
20140254317 | Correlation Techniques for Passive Electroseismic and Seismoelectric Surveying - A method for surveying, may include receiving, by a processor, first survey data from a first source, the first source comprising a first signal generated by a subsurface earth formation in response to a passive-source electromagnetic signal, wherein the electromagnetic signal is generated by an electroseismic or seismoelectric conversion of the passive-source electromagnetic signal. The method may also include receiving, by the processor, second survey data from a second source and processing the first survey data and the second survey data to determine one or more properties of a subsurface earth formation. | 09-11-2014 |
20150071033 | Correlation Techniques for Passive Electroseismic and Seismoelectric Surveying - A method for surveying, may include receiving, by a processor, first survey data from a first source, the first source comprising a first signal generated by a subsurface earth formation in response to a passive-source electromagnetic signal, wherein the electromagnetic signal is generated by an electroseismic or seismoelectric conversion of the passive-source electromagnetic signal. The method may also include receiving, by the processor, second survey data from a second source and processing the first survey data and the second survey data to determine one or more properties of a subsurface earth formation. | 03-12-2015 |
Patent application number | Description | Published |
20080307251 | FUSE FARM REDUNDANCY METHOD AND SYSTEM - A system and method for making efficient use of fuse ROM redundancy to increase yield and security. Some embodiments provide a memory repair system including a non-volatile memory component and a controller coupled to the non-volatile memory component. The non-volatile memory component includes a plurality of memory locations. The plurality of memory locations includes a replacement memory location to replace a faulty memory location and a replacement indicia memory location to store replacement memory location indicia. The controller coupled to the non-volatile memory component reads replacement memory location indicia from the replacement indicia memory location, determines an address for the replacement memory location using the indicia, reads the replacement memory location, and transfers a data value contained in the replacement memory location to a second memory component to repair a defective memory location of the second memory component. | 12-11-2008 |
20090067211 | Electronic Fuse System and Methods - An electronic fuse system and method are disclosed employing a fuse ROM having one or more blocks of memory. Each block of memory comprises a plurality of words with at least one word of the plurality of words containing security bits associated with a respective block. An electronic fuse controller is in communication with the fuse ROM and one or more external devices that are configured to request one or more words that reside in the fuse ROM from the electronic fuse controller. At least one security register includes indication bits that provide an indication whether security bits have been obtained for a respective block of memory of the fuse ROM after a power down and power up cycle. The electronic fuse controller provides the requested word if an indication bit associated with the block of memory is set. | 03-12-2009 |
20100095173 | MATRIX SYSTEM AND METHOD FOR DEBUGGING SCAN STRUCTURE - An aspect of the present invention is drawn to a system comprising an automatic test engine, a decompressor, a first scan chain, a second scan chain, a compactor and a debug output. The automatic test engine is operable to output a test output, to receive a resultant input, to receive a debug input, to monitor the debug input and to compare the test output with the resultant input. The decompressor is arranged to receive a decompressor input based on the test output, to output a decompressor output. The scan chains are arranged to receive input based on the decompressor output, and each scan chain includes at least one flip-flop. The compactor is arranged to receive input based output from the flip-flops, and to output a compactor output. The debug output line is arranged to receive the flip-flop output. | 04-15-2010 |
Patent application number | Description | Published |
20120036408 | Test Chain Testability In a System for Testing Tri-State Functionality - An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed. | 02-09-2012 |
20120079247 | DUAL REGISTER DATA PATH ARCHITECTURE - A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit. | 03-29-2012 |
20120191767 | Circuit which Performs Split Precision, Signed/Unsigned, Fixed and Floating Point, Real and Complex Multiplication - An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point data that may be single precision real, single precision complex or double precision. The circuit uses a single set of multiplier arrays to perform 16×16, 32×32 and 64×64 multiplies, 32×32 and 64×64 complex multiplies, 32×32 and 64×64 complex multiplies with one operand conjugated. | 07-26-2012 |
20130013656 | THREE-TERM PREDICTIVE ADDER AND/OR SUBTRACTER - A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2 | 01-10-2013 |
20130169332 | Family of Multiplexer/Flip-Flops with Enhanced Testability - A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter. | 07-04-2013 |
20140181165 | Three-Term Predictive Adder and/or Subtracter - A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2 | 06-26-2014 |
20150019842 | Highly Efficient Different Precision Complex Multiply Accumulate to Enhance Chip Rate Functionality in DSSS Cellular Systems - This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product. | 01-15-2015 |
20150082004 | Faster and More Efficient Different Precision Sum of Absolute Differences for Dynamically Configurable Block Searches for Motion Estimation - This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers. | 03-19-2015 |
20150154024 | Vector SIMD VLIW Data Path Architecture - A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file. | 06-04-2015 |
Patent application number | Description | Published |
20100153214 | Accessing Needs of Customers Based on Dispatched Services - Embodiments of the disclosed technology comprise a dispatch management system and method. Customer information is received by a first company and forwarded with dispatch instructions to a second company, namely, a dispatch company which handles dispatching a service technician or other support representative to the customer. The dispatch company then sends to the first company customer information regarding products and/or service related to the customer. It is then determined which products and/or services are to be advertised to the customer based on the customer information and information received from the dispatch company. Advertisements are then sent to the customer based on this determination. | 06-17-2010 |
20120004933 | System And Method For The Collection And Monitoring Of Vehicle Data - A method for brokering variable rate insurance premiums from an insurance carrier includes collecting driving information relating to a vehicle, generating a report based on the driving information, providing the driving report to the insurance carrier, receiving a revised premium based on the driving report and transmitting the revised premium to a customer. | 01-05-2012 |
20120010906 | System And Method For The Collection And Monitoring Of Vehicle Data - A method for providing a customer with a competitive insurance quote from an insurance carrier includes collecting driving information relating to a customer for a time period, generating a driving report for the time period, providing the driving report to at least two potential insurance carriers, requesting insurance bids from the potential insurance carriers, and sending at least one of the insurance bids to the customer. | 01-12-2012 |
Patent application number | Description | Published |
20110144994 | Automatic Sound Level Control - In one or more embodiments, one or more methods and/or systems described can perform determining two or more words of a written language from first data, determining at least one of a noise level external to a mobile device and a location of the mobile device, determining a sound output level based on the at least one of the noise level external to the mobile device and the location of the mobile device, and generating sound data based on the two or more words of the written language and the sound output level. The first data can include, for example, portable document format data that can include first text and/or an image that can include second text. In one or more embodiments, the location can be determined by using at least one of a global positioning system receiver and a location of an access point communicating with the mobile device. | 06-16-2011 |
20110196571 | System And Method For The Collection And Monitoring Of Vehicle Data - A communications hub for a vehicle includes a telematics device including a first communications interface to an external wireless network, a second communications interface to a plurality of vehicle sensors, and a global positioning system (GPS) interface. The telematics device is configured to (i) identify the driver of a vehicle; (ii) retrieve a profile for the driver including a profile permissions log; (iii) establish communications with the wireless network; (iv) establish communications with the vehicle sensor; (v) gather location information from the GPS interface; (v) collect data from a plurality of vehicle sensors; and (vi) send the collected data to an external recipient based on the profile permissions log. | 08-11-2011 |
20130231921 | Automatic Sound Level Control - A method includes identifying, at a computing device, a plurality of words in data. Each of the plurality of words corresponds to a particular word of a written language. The method includes determining a sound output level based on a location of the computing device. The method includes generating sound data based on the sound output level and the plurality of words identified in the data. | 09-05-2013 |