Patent application number | Description | Published |
20140122003 | PREDICTION METHOD FOR SUN-TRACKING TYPE PHOTOVOLTAIC SYSTEM - A method for predicting power generation for a sun-tracking type photovoltaic system. A calculating device may perform the prediction method and may comprise the steps of: forming a mathematical relationship that relates the variation in sunlight incident angle of powers for sun-tracking type and fixed-type photovoltaic systems to at least one electrical characteristic of the photovoltaic system; accumulating ratios between the power production rate of the sun-tracking type photovoltaic system and the fixed-type photovoltaic system; and according to a predetermined cost estimation structure, providing an analysis for determining whether a sun-tracking type photovoltaic system should be installed. | 05-01-2014 |
20140238755 | OMNI-DIRECTIONAL TERRAIN CROSSING MECHANISM - The present disclosure provides an omni-directional terrain crossing mechanism, including a transformable mechanism with a plurality of claw wheels, in order to be capable of fast moving on the flat ground or in uneven terrain environments. The omni-directional terrain crossing mechanism includes a first body and a second body. Each of the first body and the second body includes at least one pair of claw wheels. Moreover, the omni-directional terrain crossing mechanism is capable of transforming one pair of first claw wheels of the first body and one pair of second claw wheels of the second body into a pair of complete wheels. Consequently, as compared with the existing mobile machines, the omni-directional terrain crossing mechanism in the present disclosure is capable of moving in various challenging terrain environments. | 08-28-2014 |
20150024472 | BIOLOGICAL GROWTH MONITORING AND PARAMETER EXTRACTION SYSTEM - A biological growth monitoring and parameter extraction system includes a comparison group platform and an experimental group platform. First environmental sensing modules of the comparison group platform extracts first environmental parameters of a biological comparison area, a first control module transmits the parameters to the experimental group platform, and a first biological inspection module extracts growth conditions of organisms of the biological comparison area. A biological experiment area of the experimental group platform emulates growth environment of the biological comparison area, second environmental sensing modules extract second environmental parameters of the biological experiment area, and the first environmental parameters are used as reference inputs of the experimental group platform, so as to enable the second control module to obtain an error value by comparing the second and the first environmental parameters. | 01-22-2015 |
Patent application number | Description | Published |
20080217734 | Multi-level electrical fuse using one programming device - A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels. | 09-11-2008 |
20100123505 | ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT - A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH. | 05-20-2010 |
20100124099 | 8T LOW LEAKAGE SRAM CELL - This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation. | 05-20-2010 |
20110235448 | USING DIFFERENTIAL SIGNALS TO READ DATA ON A SINGLE-END PORT - In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the data on the local bit line to a global bit line. A neighbor global bit line is used as a reference for a global sense amplifier to read the differential data on the global bit line and the neighbor global bit line. | 09-29-2011 |
20120099382 | READING MEMORY DATA - A circuit includes a reference data line configured to receive a reference voltage value, a memory cell, a data line coupled to the memory cell and configured to have a data logic value associated with data stored in the memory cell, a first circuit coupled to the reference data line and to the data line, and an output node configured to selectively receive the data logic value from the data line or receive the data logic value through the first circuit, based on the reference voltage value and a trip point used to trigger the first circuit to provide the data logic value through the first circuit. | 04-26-2012 |
20120243290 | MULTI-LEVEL ELECTRICAL FUSE USING ONE PROGRAMMING DEVICE - A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels. | 09-27-2012 |
20120306537 | ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT - A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL. | 12-06-2012 |
20130194880 | READING MEMORY DATA - A circuit includes a memory array comprising K number of rows. The circuit further including a reference column. The reference column includes M cells of a first cell type configured to provide a first leakage current, K-M cells of a second cell type different from the first cell type, the K-M cells are configured to provide a second leakage current, and a reference data line connected to the cells of the first cell type and the cells of the second cell type. The circuit further includes a sensing circuit configured to determine a value stored in a memory cell of the memory array based on a voltage of the reference data line. | 08-01-2013 |
20140146619 | MEMORY WRITE ASSIST - A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell. | 05-29-2014 |
20140247672 | READING MEMORY DATA - A circuit includes one or more memory cells, a data line associated with the one or more memory cells, one or more reference cells, a reference data line associated with the one or more reference cells, a first circuit coupled to the reference data line and the data line, and a second circuit. The first circuit is configured to output a first logical value based on a voltage level of the data line upon occurrence of a voltage level of the reference data line reaching a trip point. The second circuit is configured to output a second logical value based on the voltage level on the data line prior to the occurrence of the voltage level of the reference data line reaching the trip point, and to output the first logical value after the occurrence of the voltage level of the reference data line reaching the trip point. | 09-04-2014 |